IBM Creates First 2nm Chip
by Dr. Ian Cutress on May 6, 2021 6:00 AM EST
Every decade is the decade that tests the limits of Moore’s Law, and this decade is no different. With the arrival of Extreme Ultra Violet (EUV) technology, the intricacies of multipatterning techniques developed on previous technology nodes can now be applied with the finer resolution that EUV provides. That, along with other more technical improvements, can lead to a decrease in transistor size, enabling the future of semiconductors. To that end, Today IBM is announcing it has created the world’s first 2 nanometer node chip.
Names for Nodes
Just to clarify here, while the process node is being called ‘2 nanometer’, nothing about transistor dimensions resembles a traditional expectation of what 2nm might be. In the past, the dimension used to be an equivalent metric for 2D feature size on the chip, such as 90nm, 65nm, and 40nm. However with the advent of 3D transistor design with FinFETs and others, the process node name is now an interpretation of an ‘equivalent 2D transistor’ design.
Some of the features on this chip are likely to be low single digits in actual nanometers, such as transistor fin leakage protection layers, but it’s important to note the disconnect in how process nodes are currently named. Often the argument pivots to transistor density as a more accurate metric, and this is something that IBM is sharing with us.
Transistor Density
Today’s announcement states that IBM’s 2nm development will improve performance by 45% at the same power, or 75% energy at the same performance, compared to modern 7nm processors. IBM is keen to point out that it was the first research institution to demonstrate 7nm in 2015 and 5nm in 2017, the latter of which upgraded from FinFETs to nanosheet technologies that allow for a greater customization of the voltage characteristics of individual transistors.
IBM states that the technology can fit ’50 billion transistors onto a chip the size of a fingernail’. We reached out to IBM to ask for clarification on what the size of a fingernail was, given that internally we were coming up with numbers from 50 square millimeters to 250 square millimeters. IBM’s press relations stated that a fingernail in this context is 150 square millimeters. That puts IBM’s transistor density at 333 million transistors per square millimeter (MTr/mm2).
For comparison:
| Peak Quoted Transistor Densities (MTr/mm2) | ||||
| AnandTech | IBM | TSMC | Intel | Samsung |
| 22nm | 16.50 | |||
| 16nm/14nm | 28.88 | 44.67 | 33.32 | |
| 10nm | 52.51 | 100.76 | 51.82 | |
| 7nm | 91.20 | 237.18* | 95.08 | |
| 5nm | 171.30 | |||
| 3nm | 292.21* | |||
| 2nm | 333.33 | |||
| Data from Wikichip, Different Fabs may have different counting methodologies * Estimated Logic Density |
||||
As you can tell, different foundries have different official names with a variety of densities. It’s worth noting that these density numbers are often listed as peak densities, for transistor libraries where die area is the peak concern, rather than frequency scaling – often the fastest parts of a processor are half as dense as these numbers due to power and thermal concerns.
Stacked GAA
With regards the movement to Gate-All-Around / nanosheet transistors, while not explicitly stated by IBM, images show that this new 2nm processor is using a three-stack GAA design. Samsung is introducing GAA at 3nm, while TSMC is waiting until 2nm. Intel by contrast, we believe, will introduce some form of GAA on its 5nm process.
IBM’s 3-stack GAA uses a cell height of 75 nm, a cell width of 40 nm, and the individual nanosheets are 5nm in height, separated from each other by 5 nm. The gate poly pitch is 44nm, and the gate length is 12 nm. IBM says that its design is the first to use bottom dieletric isolation channels, which enables the 12 nm gate length, and that its inner spacers are a second generation dry process design that help enable nanosheet development. This is complimented by the first use of EUV patterning on the FEOL parts of the process, enabling EUV at all stages of the design for critical layers.
Users might be wondering why we’re hearing that IBM is the first to a 2nm chip. IBM is one of the world’s leading research centers on future semiconductor technology, and despite not having a foundry offering of their own, IBM develops IP in collaboration with others for their manufacturing facilities. IBM sold its manufacturing to GlobalFoundries with a 10 year partnership commitment back in 2014, and IBM also currently works with Samsung, and recently announced a partnership with Intel. No doubt the latter two will be partnering with IBM on some level around this new development for its viability in their own production chain.
IBM Albany Research Center
No details on the 2nm test chip have been provided, although at this stage it is likely to be a simplified SRAM test vehicle with a little logic. The 12-inch wafer images showcase a variety of different light diffractions, which likely points to a variety of test cases to affirm the viability of the technology. IBM says that the test design uses a multi-Vt scheme for high-performance and high-efficiency application demonstrations.
Wafer up close
The chip was designed and made at IBM’s Albany research facility, which features a 100,000 sq. ft. clean room. The purpose of this facility is to build on IBM’s expansive patent and licensing portfolio for collaborations with partners.
We have a set of questions with IBM’s experts awaiting response. We also now have an active invitation to go visit, as and when we can travel again.
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- TSMC Update: 2nm in Development, 3nm and 4nm on Track for 2022
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Abe Dillon - Saturday, May 15, 2021 - link
...you keep beating that straw man, buddy. We're all very impressed.Spunjji - Friday, May 7, 2021 - link
It's both. The overall design of their M1 is solid, and their ARM design team have consistently out-performed the rest of the industry for years now, both in terms of year-on-year performance increases and overall performance (for the ARM architecture). In addition to that, building a working high-performance design for a cutting-edge node isn't cheap or technically trivial; even if that was all there was to it, it would still be a technical achievement!Gondalf - Thursday, May 6, 2021 - link
I don't hink so, remember these are peak values and sram scales A LOT worse, 5nm sram have only a small increase of 20% over 7nm sram (very last Apple SOC)Actually SOCs and cpus are sram centric, in this condition the shift to 5nm means very little for many. Sure 5nm is not the reason Apple shit to in house silicon for some cheap laptops.
Intel does well developing 10nm ++ that allow a more easy manufacturing than "actual EUV" and a 15% power consumption saving over 10nm +, that have a good advantage too over plain 10nm
More or less TSMC 5nm is pretty on line with 10nm ++ from an Intel point of wiew, they have a lot of silicon capacity so a loss on logic density is negligible if they can put down the power consumption on a larger node. Better jump on 7nm or 5nm (Intel) when higher yields will are available (reliable pellicles and faster scanners).
TSMC 3nm will be even weaker than TSMC 5nm.
Tomatotech - Thursday, May 6, 2021 - link
Wow. What's in it for you? Why this desperate need to shit on TSMC and boost Intel "7nm or 5nm" which clearly you know nothing about, and nor does anybody who isn't one of the internal team directly working on these techs. Not even most Intel staff know how they will turn out.If you wanted to be an adult, just say "Intel have some excellent minds and a very powerful tech and R&D team. I'm hoping they can pull out something good for 7nm and 5nm. TSMC have done some excellent stuff and given good competition to Intel. I'm still rooting for Intel though."
See how easy it is to be competitive but still respect the other team?
Qasar - Thursday, May 6, 2021 - link
whats in it for him? nothing he just loves intel.movax2 - Thursday, May 6, 2021 - link
Intel has low yields on 10nm++(+) node. It's very easy to see as Tiger-Lake 8-cores was delayed again and again."More or less TSMC 5nm is pretty on line with 10nm ++" .... what kind of biased statement it is?
TSMC 5nm is considerably densier than Intel 10nm++(+).
melgross - Thursday, May 6, 2021 - link
You have problems sir.Spunjji - Friday, May 7, 2021 - link
"More or less TSMC 5nm is pretty on line with 10nm ++"Wrong. 10nmSF is comparable to TSMC 7nm. TSMC 5nm is far ahead in density and may well be better in power characteristics, though those are difficult to compare.
"they have a lot of silicon capacity so a loss on logic density is negligible"
Not even close. Where are all the 8-core Tiger Lake chips? 🤷♂️
Linustechtips12#6900xt - Monday, May 10, 2021 - link
I highly dought that 5nm was what made apple switch but it is an advantage, I mean the time they planned this stuff they were releasing stuff like the iPhone 7/8 and earlier probably tbhYojimbo - Thursday, May 6, 2021 - link
Intel is not 3 years behind. There are a few considerations that have to be made.Firstly, you are comparing TSMC's small chip, low power chip production with Intel's large chip, high powered production. Also, when Intel unveils a process it's when chips are being released on volume from it. TSMC talks about chips going into volume production. The Ryzen 3000 series and the Radeon 5000 series launched in July 2019, and with volume that wouldn't be enough for an Intel launch. Intel launched 10 nm chips for volume in September 2020 with Tiger Lake, although with a slower rollout than Intel would normally have for a new node (desktop won't be on 10 nm until 2H 2021). I'm sure there are various arguments to be made, but Intel's 10 nm is roughly equivalent to TSMC's 7 nm. So Intel is, at its worst, a year and a half behind TSMC by that metric, the metric of high powered chip availability, which is the metric that matters to Intel. (Intel has not been trying to push out a high volume, lower-powered node as soon as possible. That may change with their new foundry push.)
Secondly, Intel is not happy with the financial characteristics of their 10 nm node and so they have not latched onto it full force. But judging by AMD and TSMC's margins, TSMC's 7 nm is also an expensive node. Intel was not willing to sacrifice financial performance and attempted to defend its market share in other ways (with its platform approach, with the volume it can promise, and knowing that AMD would only have a limited volume to work with). AMD, on the other hand, is in a different market position. Going from 10% to 20% market share instead of 10% to 15% is much more important to them than going from 90% to 80% instead of 90% to 85% is to Intel, once the financial cost of the alternatives are considered. To defend that 5% market share, Intel would have to suffer the financial implications of the more expensive node on a lot more than just 5% of their production. Chip makers don't have much choice but to use TSMC's 7 nm node, because TSMC are not creating special version of their 16 nm node for customers the way Intel does for itself on its 14 nm node. (NVIDIA did choose to go for Samsung's 8 nm node, which is a version of their 10 nm node.)
It's these sort of considerations, for example, the market position the companies hold and what their goals are, that need to be taken into account to make a more accurate judgment on the technical position of TSMC compared to Intel.
Now, in terms of next gen, Intel's 7 nm should be compared with TSMC's 5 nm, although in this case Intel's 7 nm looks a bit ahead on paper. It's somewhere between TSMC's 5 nm and 3 nm, density-wise. Intel plans for volume chips availability of high powered chips on the 7 nm node in 2023. TSMC has 5 nm low powered chips out now and they've had them since September 2020. But as far as I know there won't be high volume availability of large, high-powered 5 nm chips until 2022. That puts TSMC about a year ahead of Intel in terms of timing, but with a process that's behind. In other words, if Intel manages to execute according to their current plan (admittedly something to give pause for doubt in light of their recent difficulties) Intel and TSMC will be roughly even.