More I/O For AM5: PCIe 5, Additional PCIe Lanes, & More Displays

AMD’s other big expenditure using socket AM5’s additional pins is on I/O support. While AM4 already supported a fair bit of I/O, including 24 PCIe lanes, 3 displays, and 4 Superspeed USB ports, there was still room for improvement. So for AM5, AMD has increased the amount of I/O and the flexibility offered with the platform.

The biggest change here is that the AM5 socket now provides for 28 lanes of PCIe, a net gain of 4 lanes. More significantly still, PCIe 5.0 is now supported (at least on the Ryzen 7000 “Raphael” processors), doubling the bandwidth of all of those PCIe lanes to a max of 4GB/sec/lane. Which gives the chip a maximum cumulative PCIe bandwidth of 112GB/sec in each direction.

In practice, those additional lanes are intended for NVMe drives, giving AM5 a second x4 connection to drive a second NVMe drive; though we have seen some motherboard designs where vendors are stealing the second x4 for a PCIe 5.0 x4 slot. Past that, things look a lot like AM4, with 16 PCIe lanes to directly drive one or more PCIe slots, and then 4 lanes for hooking up the chipset.

Meanwhile, the updated socket also offers enough pins for the CPU to drive 4 Superspeed USB 3.x ports, and a USB 2 port. The USB 2 port is new for this generation, and meanwhile 3 of those USB 3 ports now also support the USB Type-C connector, unlike AM4 which could only natively drive Type-A ports. As a result, AM5 CPUs can drive a total of 3 Superspeed Type-C ports, a fourth Superspeed Type-A port, and then the aforementioned USB 2 port.

There has been one regression, however, and that is SATA support. Whereas AM4 CPUs could drive a mix of NVMe and SATA drives (up to 2 SATA + a PCIe x2 for NVMe), AM5 is purely PCIe. So there is no native SATA support on the CPU, and supplying that will come from the chipset.

To visualize this, we’ll use part of the AM5 chipset diagram. We’ll go more into the specifics of the chipsets in a bit, but lays out what is wired to the CPU, and what will need to be wired to the chipset. Of note there, the current chipsets only use PCIe 4.0 connectivity to the Ryzen CPU, so the current generation of chipsets will not be making full use of the bandwidth capabilities of the CPU itself.

Which with the addition of PCIe 5.0 support to the platform, is going to be a recurring theme. While AMD has baked in 5.0 support into the Raphael CPUs, it’s up to motherboard vendors to actually make it so. Compared to PCIe 4.0, 5.0 has much tighter signal integrity requirements (the signaling frequency has been doubled), which at least at this time, makes PCIe 5.0 expensive to implement. A very well-designed motherboard is required with impeccable traces, and on top of that the overall short throw of PCIe 5.0 means that retimers/redrivers become necessary rather quickly. So while AM5 can support PCIe 5.0 throughout, the reality is that we’re still going to see a lot of PCIe 4.0 in use even in higher-end motherboards.

As for the necessity of PCIe 5.0 overall, thus far AMD is primarily focused on what it means for NVMe drive speeds. The first generation of PCIe 5.0-enabled consumer SSDs are expected to land a bit later this year, and they should be able to hit sequential burst transfer rates above the limits of PCIe 4.0 (~7GB/sec).

Past that, NVIDIA’s newly announced Ada Lovelace architecture GeForce RTX 40 series video cards do not support PCIe 5.0. So while we’re awaiting AMD to announce their RDNA 3-based product lineup later this year, regardless of what AMD does, the bulk of video cards sold next year are not going to use PCIe 5.0. So there is a bit less pressure on motherboard manufactures (and motherboard buyers) to get boards that support PCIe 5.0 to anything beyond a couple of M.2 slots.

Finally, in conjunction with the USB I/O changes, AM5 also introduces some display I/O changes. Whereas AM4 could directly drive up to 3 displays, AM5 brings this to 4. Specifically, AM5 offers one dedicated display output (which will generally be allocated to HDMI), while the other 3 display outputs are available over those 3 USB Type-C ports as DisplayPort alt mode. It’ll be up to motherboard manufacturers if they want to expose any of these USB-C root ports as physical USB-C ports or as DisplayPorts, but so far from the motherboard designs we’ve seen, the former is more common (though certainly not universal).

Anticipating a shift to more USB Type-C displays, AMD is also implementing what they call “hybrid graphics” support on AM5. Unlike previous products where this referred to linking up the integrated graphics with a discrete GPU in CrossFire mode, this time around it refers to being able to being able to use the mobo/iGPU’s display outputs to drive a monitor while using a dGPU to render content. This is largely lifted from AMD’s laptop technologies, where similar techniques are used to allow the dGPU to be powered down when it’s not in use. In the case of desktop processors, this just means every display output will work, regardless of whether it’s plugged into ports coming from the CPU or a discrete video card.

It’s also worth noting that AM5 is bringing a few other, more minor updates to other comms protocols. Among these is support for MIPI’s (relatively) new I3C chip-to-chip signaling standard, which will ultimately be supplanting the long-used I2C standard. As well, AM5 doubles the number of I2C/I3C ports available, bringing the total to 4 ports. The platform also adds a second (enhanced) Serial Peripheral Interface (eSPI/SPI) port, and on the audio front, adds support for the Digital Mic and MIPI’s Soundwire standard for low-cost audio peripherals.

Socket AM5: The New Platform for Consumer AMD AM5 Chipsets: X670 and B650, Built by ASMedia
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  • AndrewJacksonZA - Monday, September 26, 2022 - link

    I would imagine it's a technically correct way of saying that it's certified for Windows 11. See here about the TPM:
    www DOT microsoft DOT com/security/blog/2020/11/17/meet-the-microsoft-pluton-processor-the-security-chip-designed-for-the-future-of-windows-pcs/
    Reply
  • socket420 - Monday, September 26, 2022 - link

    I'm primarily asking whether or not the Pluton security coprocessor has been incorporated into Raphael/Ryzen 7000 CPUs, and I'm pretty sure that isn't what they were implying - Microsoft *does* have a "secured-core PC" baseline for Win11 they've been pushing lately, but it's currently unclear how Pluton ties into that so I don't think Win11 "certification" has anything to do with it. Pluton wasn't mentioned in AMD's desktop Ryzen 7000 press release last month, I didn't see it in any of the Zen 4 architectural slides they showed off today and AnandTech is the only outlet that's brought it up at all, which is why I'm asking this question in the first place - AMD hasn't been particularly forthcoming about the subject and I feel like they would've mentioned Pluton in a press release if it was actually present in these chips. Reply
  • Ryan Smith - Monday, September 26, 2022 - link

    I am not privy to the implementation details. But like other parts of the IOD, Pluton is inherited from the Ryzen 6000 Mobile parts. So it has the same Pluton implementation as those mobile chips.

    TL;DR: I don't know how they're technically accomplishing it, but yes, Pluton is there and enabled.
    Reply
  • socket420 - Tuesday, September 27, 2022 - link

    Thanks for the response. Just to clarify, if I reread that section correctly, the Ryzen 7000 I/O die is a new design that had most of the additions from Ryzen 6000 ported over to it, Pluton included. That sounds incredibly damning, but I'm not sure how it's possible to confirm its presence without implementation details. I'm also unsure why AMD would brag about Pluton being present in two different mobile CPU releases from the moment they were announced while seemingly ignoring it in their new and shiny desktop Ryzen lineup up until its release date (are they hoping we won't notice?), but then again, it's been months since Ryzen 6000 was launched and no one's taken a closer look at its Pluton implementation yet, so :/

    IIRC, Lenovo ships their Ryzen 6000 Thinkpads with Pluton disabled and you have to go into their BIOS to toggle it on or off, so maybe that option showing up on consumer AM5 boards will show us if Pluton's there or not? It'd also be cool if someone asked AMD directly for a response, but Robert Hallock said he "didn't know" if Pluton was in Zen 4 and he coincidentally just left the company, so I have no idea who to reach out to.
    Reply
  • Silver5urfer - Tuesday, September 27, 2022 - link

    Thanks for your question and this new garbage Pluton cancer is what I did not want to see shame how they added it. Reply
  • Oxford Guy - Tuesday, September 27, 2022 - link

    You will own nothing and be owned by everything. You will be happy. Reply
  • Valantar - Monday, September 26, 2022 - link

    Could you please run your per-core power draw tests for these chips like you did for Zen3? Reply
  • takling1986 - Monday, September 26, 2022 - link

    I think this review is "streets ahead". Reply
  • IBM760XL - Monday, September 26, 2022 - link

    All right, since they aren't read yet, I'll ask... is it easy to set a lower TDP limit, and could you examine power efficiency when the TDP is the same as it was for Ryzen 5000?

    Looking at the numbers Tom's Hardware posted, the 7950X uses about 80W more at load than the 5950X. With AMD's own slides touting the efficiency improvements being greater at lower TDPs, what I'd really like is to have an octo-core at 65W like the 5700, or perhaps a 12/16 core at 105W like the 5900/5950.

    Though I'm very likely to wait until B650 drops before making a decision, so there's plenty of time for an answer to that question to arrive.
    Reply
  • abufrejoval - Wednesday, September 28, 2022 - link

    I can only guess that it should be trival to do via RyzenMaster, just in case it's not supported in the BIOS. And of course I'd demand CLI tools for both Linux and Windows.

    I cannot imagine that with a max TDP of 140 Watts a 7950X won't still be faster than a 5950X, even if it won't be quite as fast as if you let it drain the bottle at full hilt. The typical CMOS knee will still be there, only moved forward a bit and with a lot more of a "hot leg" showing towards the top.

    But gains per clock and Watt will be terrible the higher you go on the "hot leg" by nature of silicon physics and any sensible person will just use a "lesser cooler" to avoid that nonsense.
    Reply

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