TSMC this week announced a new fabrication process that is tailored specifically for high-performance computing (HPC) products. N4X promises to combine transistor density and design rules of TSMC's N5-family nodes with the ability to drive chips at extra high voltages for higher frequencies, which will be particularly useful for server CPUs and SoCs. Interestingly, TSMC's N4X can potentially enable higher frequencies than even the company's next-generation N3 process.

One of the problems that is caused by shrinking sizes of transistors is shrinking sizes of their contacts, which means increased contact resistance and consequent problems with power delivery. Various manufacturers use different ways of tackling the contact resistance issue: Intel uses cobalt contacts instead of tungsten contacts, whereas other makers opted to forming contacts using selective tungsten deposition technology. While these methods work perfectly for pretty much all kinds of chips, there are still ways to further improve power delivery for high-performance computing (HPC) designs, which are relatively immodest about the total about of power/voltage being used. This is exactly what TSMC did to its N4X node. But before we proceed to details about the new fabrication process, let us see what advantages TSMC promises with it. 

TSMC claims that its N4X node can enable up to 15% higher clocks compared to a similar circuit made using N5 as well as an up to 4% higher frequency compared to an IC produced using its N4P node while running at 1.2V. Furthermore – and seemingly more important – N4X can achieve drive voltages beyond 1.2V to get even higher clocks. To put the numbers into context: Apple's M1 family SoCs made at N5 run at 3.20 GHz, but if these SoCs were produced using N4X, then using TSMC's math they could theoretically be pushed to around 3.70 GHz or at an even higher frequency at voltages beyond 1.2V.

TSMC does not compare transistor density of N4X to other members of its N5 family, but normally processors and SoCs for HPC applications are not designed using high-density libraries. As for power, drive voltages of over 1.2V will naturally increase power consumption compared to chips produced using other N5-class nodes, but since the node is designed for HPC/datacenter applications, its focus is to provide the highest performance possible with power being a secondary concern. In fact, total power consumption has been increasing on HPC-class GPUs and similar parts for the last couple of generations now, and there is no sign this will stop in the next couple of generations of products, thanks in part to N4X.

"HPC is now TSMC's fastest-growing business segment and we are proud to introduce N4X, the first in the ‘X’ lineage of our extreme performance semiconductor technologies," said Dr. Kevin Zhang, senior vice president of Business Development at TSMC. "The demands of the HPC segment are unrelenting, and TSMC has not only tailored our ‘X’ semiconductor technologies to unleash ultimate performance but has also combined it with our 3DFabric advanced packaging technologies to offer the best HPC platform."

Advertised PPA Improvements of New Process Technologies
Data announced during conference calls, events, press briefings and press releases
  TSMC
N5
vs
N7
N5P
vs
N5
N5HPC
vs
N5
N4
vs
N5
N4P
vs
N5
N4P
vs
N4
N4X
vs
N5
N4X
vs
N4P
N3
vs
N5
Power -30% -10% ? lower -22% - ? ? -25-30%
Performance +15% +5% +7% higher +11% +6% +15%
or
more
+4%
or more
+10-15%
Logic Area

Reduction %

(Density)
0.55x

-45%

(1.8x)


-


-
0.94x

-6%

1.06x
0.94x

-6%

1.06x


-


?


?
0.58x

-42%

(1.7x)
Volume
Manufacturing
Q2 2020 2021 Q2 2022 2022 2023 H2 2022 H1
2024?
H1 2024? H2 2022

In a bid to increase performance and make drive voltages of over 1.2V possible, TSMC had to evolve the entire process stack.

  • First, it redesigned its FinFET transistors and optimized them both for high clocks and high drive currents, which probably means reducing resistance and parasitic capacitance and boosting the current flow through the channel. We do not know whether it had to increase gate-to-gate pitch spacing and at this point TSMC does not say what exactly it did and how it affected transistor density.
  • Secondly, it introduced new high-density metal-insulator-metal (MiM) capacitors for stable power delivery under extreme loads.
  • Thirdly, it redesigned back-end-of-line metal stack to deliver more power to transistors. Again, we do not know how this affected transistor density and ultimately die sizes.

To a large degree, Intel introduced similar enhancements to its 10nm Enhanced SuperFin (now called Intel 7) process technology, which is not surprising as these are natural methods of increasing frequency potential.

What is spectacular is how significantly TSMC managed to increase clock speed potential of its N5 technology over time. A 15% increase puts N4X close to its next-generation N3 fabrication technology. Meanwhile, with drive voltages beyond 1.2V, this node will actually enable higher clocks than N3, making it particularly good for datacenter CPUs.

TSMC says that expects the first N4X designs to enter risk production by the first half of 2023, which is a very vague description of timing, as it may mean very late 2022 or early 2023. In any case, it usually takes a year for a chip to proceed from risk production to high-volume production iteration, so it is reasonable to expect the first N4X designs to hit the market in early 2024. This is perhaps a weakness of N4X as by the time its N3 will be fully ramped and while N4X promises to have an edge in terms of clocks, N3 will have a major advantage in terms of transistor density.

Source: TSMC

POST A COMMENT

42 Comments

View All Comments

  • Kevin G - Friday, December 17, 2021 - link

    “Apple's M1 family SoCs made at N5 run at 3.20 GHz, but if these SoCs were produced using N4X, then using TSMC's math they could theoretically be pushed to around 3.70 GHz or at an even higher frequency at voltages beyond 1.2V.”

    The big thing missing for context on this is simply what voltage does the M1 currently operate at? Say if it is 1.0V, then moving to the N4X process would result in a ~66% increase in power consumption for a meager ~16% increase in performance. For a chip targeted at mobile, that’d be a bad move give the emphasis on performance per watt.

    For the targeted markets, it’ll be attractive and those who need maximum performance regardless of power consumption.

    We’re also entering an era where chiplets are the norm so targeting (relatively) high voltages and clock focused manufacturing nodes to the specific aspects if a design is feasible. Things like stacked cached can continue to be made on more commodity nodes or IO coming from more analog friendly nodes etc. I have a feeling that if such advanced packing techniques were not going to be common in the HPC sector, we likely wouldn’t have seen this node as it’d be too crazy for a large monolithic design ( >500 mm^2 ).
    Reply
  • Alistair - Friday, December 17, 2021 - link

    not true, you'd expect better frequencies all along the voltage curve... Reply
  • brucethemoose - Friday, December 17, 2021 - link

    Not necessarily along the whole voltage curve, but probably at the tail end, yeah. Reply
  • Hul8 - Saturday, December 18, 2021 - link

    > For a chip targeted at mobile, that’d be a bad move give the emphasis on performance per watt.

    I think the implication in the article was "if Apple decides they want workstation or server CPUs using the ARM architecture".
    Reply
  • Kevin G - Saturday, December 18, 2021 - link

    I get there but when we’re in the era of chiplets, what is the better path to performance: going to higher voltages and clicks to increase single threaded performance or to increase core counts given the same power envelope as the voltage/clocks? 66% more cores or 16% or higher clocks? For the server market it’d be more cores. For the workstation market is probably the sole niche where the higher clock trade off makes sense given their workloads. Their is a desire for more cores in workstations up to a point. However the workstation market isn’t large enough by itself to make a specialized N4X processor chiplet vs. a more mobile or density focused node. We’ll continue to see high end desktop and low end server gear be repurposed for the traditional workstation. Reply
  • whatthe123 - Sunday, December 19, 2021 - link

    you already have many-core designs floating in the wild with 100+ cores. it doesn't necessarily scale better even with the core advantage, probably because data access times becomes a problem. cache isn't shrinking nearly at the same pace as logic on modern nodes so it makes sense to fatten cores to a certain extent for fast single thread processing. cloud is the main market for shoving in a billion cores, but it's just one of many enterprise markets. Reply
  • dotjaz - Sunday, December 19, 2021 - link

    The most ridiculous part is that's mere 4% increase over N4P, entirely pointless if the figures are true. Reply
  • mode_13h - Saturday, January 1, 2022 - link

    That would also seem to depend on pricing, production capacity, and yield. Reply
  • Alistair - Friday, December 17, 2021 - link

    5.30Ghz all core Ryzen CPUs? Sign me up! :) Reply
  • evanh - Friday, December 17, 2021 - link

    I was under the impression that High-Performance-Computing is completely different to data centre servers. As far as I was aware, your typical web/file server is all about power efficiency. - The amount of compute per Watt. Under-clocking is the name of the game there. Reply

Log in

Don't have an account? Sign up now