Exploring DynamIQ and ARM’s New CPUs: Cortex-A75, Cortex-A55by Matt Humrick on May 29, 2017 12:00 AM EST
- Posted in
- Cortex A75
- Cortex A55
ARM moves at an aggressive pace, pushing out new processor IP on a yearly cadence. It needs to move fast partly because it has so many partners across so many industries to keep happy and partly because it needs to keep up with the technology its IP comes into contact with, everything from new process nodes to higher quality displays to artificial intelligence. To keep pace, ARM keeps multiple design teams in several different locations all working in parallel.
At its annual TechDay event last year, held at one such facility in Austin, Texas, ARM introduced the Mali-G71 GPU—the first to use its new Bifrost GPU architecture—and the Cortex-A73 CPU—a new big core to replace the A72 in mobile. Notably absent, however, was a new little core.
Another year, another TechDay, and another ARM facility (this time in Cambridge, UK)—can only mean new ARM IP. Over the span of several days, we got an in-depth look at its latest technologies, including DynamIQ, the Mali-G72 GPU, the Cortex-A75, and (yes, finally) the successor to the A53: Cortex-A55.
The A53 was announced alongside the A57 and has been in use for several years, both on its own or as the little core in a big.LITTLE configuration. It’s been hugely successful, with more than 40 licensees and 1.7 billion units shipped in just 3 years. But during this time ARM introduced new big cores on a yearly cadence, moving from A57 to A72 to A73. The A53 remained unchanged, however, even as the performance gap between the big and little cores continued to grow.
Predictably then, the focus for A55 was on improving performance. The A53’s dual-issue, in-order core, which serves as the starting point for A55, already delivers good throughput, so ARM focused on improving the memory system. A new data prefetcher, an integrated L2 cache that reduces latency by 50%, and an extra level of L3 cache (among other changes) give the A55 significantly better memory performance—quantified by a nearly 2x improvement in the LMBench memory copy test. The numbers provided by ARM also show an 18% performance gain in SPECint 2006 and an even bigger 38% gain in SPECfp 2006 relative to the A53. These numbers, as well as the others shown in the chart, comparing the A55 and A53 are at the same frequency, same L1/L2 cache sizes, same compiler, etc. and are meant to be a fair comparison. The actual gains should actually be a little higher, because partner SoCs will benefit from adding the L3 cache, which these numbers do not include.
The additional performance does not come for free, however. Power consumption is up 3% relative to the A53 (iso-process, iso-frequency), but power efficiency still improves by 15% when running SPECint 2000 because of its higher performance.
The A55 includes several new features too that will help it expand into new markets. Virtual Host Extensions (VHE) are very important for the automotive market and the advanced safety and reliability features, including architectural RAS support and ECC/parity for all levels of cache are critical for many applications, including automotive and industrial. There’s new features for infrastructure applications too, including a new Int8 dot product instruction (useful for accelerating neural networks). Because A55 is compatible with DynamIQ, it also gets cache stashing and access to a 256-bit AMBA 5 CHI port.
When ARM announced the A73 last year, it talked a lot about improving sustained performance and working within a tight thermal envelope. In other words, the A73 was all about improving power efficiency. The A75 goes in a different direction: Taking advantage of the A73’s thermal headroom, ARM focused on improving performance while maintaining the same efficiency as the A73.
Our previous performance testing revealed mixed results when comparing the A73 to the A72—not too surprising given the significant differences in microarchitecture—with the A73 generally outpacing the A72 by a small margin for integer tasks but falling behind the older CPU in floating point workloads. Things look better for the A75, at least based on ARM’s numbers, which show noticeable gains over the A73 in both integer and floating-point workloads as well as memory streaming.
The graph above shows that the A75 operating at 3GHz on a 10nm node achieves better performance and the same efficiency as an A73 operating at 2.8GHz on a 10nm node, which means the A75 consumes more power. How much more is difficult to tell based on this one simple graph. We know that the A73 is thermally limited when using 4 cores (albeit less so than the A72), so the A75 definitely will be as well. This is not a common scenario, however. Most mobile workloads only fire up 1-2 cores at a time and usually only in short bursts. ARM obviously felt comfortable enough using the A73’s extra thermal headroom to boost performance without negatively impacting sustained performance.
ARM wants to push the A75 into larger form-factor devices with power budgets beyond mobile’s 750mW/core too by pushing frequency higher. Something like a Chromebook or a 2-in-1 ultraportable come to mind. At 1W/core the A75 delivers 25% higher performance than the A73 and at 2W/core the A75’s advantage bumps up to 30% when running SPECint 2006. If anything, these numbers highlight why it’s not a good idea to push performance with frequency alone, as dynamic power scales exponentially.
ARM targeted the A73 specifically at mobile by focusing on power efficiency and removing some features useful for other applications to simplify the design, including no ECC on the L1 cache and no option for a 256-bit AMBA 5 CHI port. With A75, there’s now a clear upgrade path from A72. For the server and infrastructure markets, A75 supports ECC/parity for all levels of cache and AMBA 5 CHI for connecting to larger CCI, CCN, or CMN fabrics, and for automotive and other safety critical applications there’s architectural RAS support, protection against data poisoning, and improved error management.
On the next few pages, we’ll dive deeper into the technical details and features of ARM’s new IP, including DynamIQ (the next iteration of big.LITTLE), Cortex-A75, and Cortex-A55.
Post Your CommentPlease log in or sign up to comment.
View All Comments
Krysto - Monday, May 29, 2017 - linkI don't think these chips will ship by late 2018. ARM typically announces its chips 2 years before they are shipped. To be shipped in early 2018, there would have to already be a Cortex A75 tapeout, which I don't think is the case. In 2019, Samsung likely intends to release Galaxy S10 with 7nm chips, so I'm going to assume it will be the A75.
jjj - Monday, May 29, 2017 - linkThis is aimed at 10nm and the cycle that starts in early 2018 or before. So SD845 at MWC 2018 and maybe Huawei does it again and has something this year.
The slides mention 10nm but not 7nm, the article notes repeatedly late 2017-early 2018.
A73 was announced a year ago and Huawei had Kirin 960 last year, Qualcomm in first half of 2017.
This is an unveiling for the public not ARM's partners.
Also do remember that ARM has a new big core every year now.
As for Samsung, they'll likely stick with their own core next year and remains to be seen what ARM has for 7nm.
It appears that the Austin team got an extra year to work on the next core and that could be a hint that the core aimed at 7nm is an entirely new design.
aryonoco - Monday, May 29, 2017 - linkYou have obviously not read this article then.
These IPs will be seen in SoCs in late this year/early next year.
nandnandnand - Monday, May 29, 2017 - link15 W TDP you say... maybe 8x 2 Watt A75s crammed into one laptop?
jjj - Monday, May 29, 2017 - linkDo note that the numbers ARM quotes are for just the core, no cache, interconnect, IO, GPU.
A SoC with 4x2W would use quite a bit more power than just 8W.
Krysto - Monday, May 29, 2017 - linkSadly, I think DinamiQ doesn't mean that chip makers will use a single 8-core cluster, but that they will use both DinamiQ and big.Little in configurations like 2+8 or 4+8, or even 8+8, mainly for marketing reasons. So the performance flexibility won't change much.
phoenix_rizzen - Monday, May 29, 2017 - linkDynamIQ and big.LITTLE are not compatible, you can't mix and match. You either use older cores (A72/73 + A53) with big.LITTLE, or you use newer cores (A75+A55) with DynamIQ.
DynamIQ, IIUC, allows for multiple clusters, so you could get 8+8, 4+8, 2+8 and similar configurations. I doubt anyone would do that in a smartphone; but the Chinese OEMs seem obsessed with core counts, so they may do something weird (like the Helio tri-cluster setup).
twotwotwo - Monday, May 29, 2017 - linkWhat is branch prediction used for in the *in-order* A55? Is it just to try to prefetch the right instructions into L1I? Or can you do some speculative stuff (e.g. decode the expected next instruction) and still be called in-order?
Wilco1 - Monday, May 29, 2017 - linkIn-order doesn't imply no speculation. Instructions after a branch start executing speculatively but cannot complete until the branch direction is determined.
Branch prediction is as important for an in-order core as it is for an OoO core. Without branch prediction every branch would take 8+ cycles rather than < 0.1 cycles on average.
alpha64 - Monday, May 29, 2017 - linkI am a bit confused by this statement on the second page:
"Together with L3 cache and other control logic, the DSU is about the same area as an A55 core in its max configuration or half the area of an A55 in its min configuration."
Is this backwards (half A55 in max, or ~A55 in min), or is the second A55 supposed to be an A75?