In a publicly available document, found by an eagle-eyed user on Twitter, Cisco has revealed some details about the future Whitley Platform and Barlow Pass: the set of technologies on which Cooper Lake and Ice Lake Xeon Scalable will be based.

The document detailing Cisco’s Unified Computing System, was published in December 2018 for Cisco customers to plan their future upgrade strategy. The document focuses on Cisco’s networking portfolio, as one might have assumed, but also shows a roadmap on the company’s current M5 server platform and the upcoming M6 platform.

Cisco is listing its M6 server platform, for Cooper Lake and Ice Lake, as expecting to be launched in the first half of 2020. This is on par with our estimates, although perhaps a bit slow for Cooper Lake given that Intel has already shown roadmaps indicating that Cooper Lake is a 2019 platform (clearly, a late 2019).

The Whitley Platform will follow the Purley Platform, and this document confirms that Whitley (which has both Cooper Lake and Ice Lake in support) will have 8 channels of DDR4 supporting up to DDR4-2933 memory. This will require a new socket for the extra channels, which we know as LGA4189, and will put Intel on par with AMD’s EPYC platform in channel count.

The document also sheds some light on Intel’s PCIe strategy. We have already seen that AMD will launch its new Rome processors in 2019 with PCIe 4.0 support, and Intel will follow that with Cooper Lake and Ice Lake, however it looks as if Intel will bifurcate this strategy. This document lists Cooper Lake as PCIe 3.0/4.0, which might suggest that there will be two different versions, or that it will be rated PCIe 3.0 to start and 4.0 will come later. We are not sure, however it does list Ice Lake as PCIe 4.0 out of the gate.

It is worth noting that the motherboards for Whitley will support Cooper Lake and Ice Lake, so they will have to cater for PCIe 4.0 straight out of the gate. If Cooper Lake does come out with PCIe 3.0 only parts, we may see motherboards that only support PCIe 3.0 for specific customers (much like when we have a DDR memory change). This is unclear at this point.

It is worth noting that this document misspells Cooper Lake as Copper Lake. Given that this is an official document we expect this is only a typographical error. It also doesn't list the process technologies for Cooper and Ice, even though they had been announced in December. This is likely just a delay of information propagation. 

Source: Cisco

Title image from Intel's Architecture Day, showing an Ice Lake Xeon Scalable LGA4189 processor

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  • Kevin G - Wednesday, February 6, 2019 - link

    The former EX line up was generally good for three generations. (Sandy Bridge-EX was skipped but would have fit into the same socket at Westmere-EX).

    Purely merged Intel's dual/quad EP platform with the quad/octo/more EX segment. What got skipped is Cannon Lake-SP which was pretty clear early on wouldn't make it due to 10 nm delays.

    Cascade Lake is indeed a minor bump but it fixes some errata regarding Optane DIMMs. I know of a few big data people who are eager to leverage cheap (to DRAM at least) 512 GB modules in an 8 way server to attempt things like running large Hadoop data sets on a single node instead of a cluster. Even though the Optane DIMMs are going to be chronically slow compared to DRAM, they should still beat a network operation that has to jump between nodes.

    There is a slim chance that Cooper Lake could still appear on socket LGA 3647 to keep various OEMs happy. This would be similar to how Intel releases the the same die between LGA 3647 and LGA 2066 today based upon market segment.

    The real wild card is what will replace Cascade Lake-AP for HPC and if it'll use the same socket.

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