I’m pretty sure that the next time I go to a trade show where new silicon is being announced, the next tool I need in my backpack is a set of calipers in order to measure the die size. While die size doesn’t in of itself mean much as a number on its own, it is the end result of lots of hard work, focused co-design between silicon engineers and the semiconductor fabs, and ultimately there’s a fine balance between features, die size, performance, power, and at the end of the day, cost. With AMD showcasing the first x86-based 8-core CPU to move into the 15 W power envelope, finding out the die size is one of the elements of our investigation into how AMD has created its new Renoir / Ryzen Mobile 4000 product.

When I first saw the silicon, I wasn’t able to take pictures. Instead, I had to guess the size by manually placing it next to a 8-core Zen 2 chiplet from AMD’s monster 64-core Threadripper 3990X. We’ve known the die size for a while now, at 10.32 x 7.34 mm, or 75.75 mm2. My guess at the time that the new Renoir APU was almost exactly double the Zen 2 chiplet, and I mean it was scary how close to double the size it was. At the time of the announcement of Ryzen Mobile 4000, I had stated in our article that I estimated 150 mm2 for the die size. Turns out, I wasn’t too far wrong.

This image is not to scale.

Later at CES, I went up to the AMD booth and this time they were more than happy for me to take photographs of the new silicon. The 3990X was also there, so I could place the two side by side and get a reasonable reference photograph on which to do calculations. This is the point of the event where I should have remembered to bring calipers! Taking photographs of chips is actually quite hard, making sure you get them lined up perfectly to get the same perspective, but also having enough light to get clear defined silicon edges.

In our picture, the Renoir chiplet you may notice is very slightly angled to the camera, which we’ve compensated for in our measurements.

With that in mind, here are our numbers.

The Zen 2 chiplet on the left, measures 10.32 mm by 7.34 mm, which is a ratio of 1.406 to 1.
In our image, the chiplet measured 265 pixels by 189 pixels, which is a ratio of 1.402 to 1.

In our image, the Renoir SoC measured 282 pixels by 350 pixels, which is a ratio of 0.806 to 1.
If we take the corresponding pixel dimensions, that gives us 10.98 mm by 13.59 mm, a ratio of 0.808 to 1.

This means that the die size of an eight-core Renoir APU with eight 2nd Gen Vega compute units, according to our calculations, 149.27 mm2.

Die Sizes
AnandTech x y Die Size Process Cores EUs/
AMD Zen 2 Chiplet 10.32 7.34 75.75 mm2 TSMC N7 8 -
Intel Ice Lake 11.44 10.71 122.52 mm2 Intel 10 4 64
Intel Tiger Lake 13.64 10.71 146.10 mm2 Intel 10+ 4 96
AMD Picasso 19.21 10.92 209.78 mm2 GF 12 4 11
AMD Renoir APU 13.59 10.98 149.22 mm2 TSMC N7 8 8

That’s pretty close to my 150 mm2 estimate, and I’ve also spoken to a few trusted individuals who have been tracking Zen 2 die structure sizes and graphics structure sizes, and they came out very similar, within 1mm2 or so.

At 149.27 mm2, assuming that AMD is achieving the same defect ratio on the silicon as reported by TSMC for the standard N7 process (0.09 defects per cm2), the process yield should be around 90%. Obviously that doesn’t take into account manufacturing for yield, or the distribution of the power/frequency of the chips within a wafer, but it’s still rather impressive.

Before AMD announced this new chip, there was a good deal of speculation as to how AMD would build it: either four cores with more graphics, or with eight cores and graphics only a little better. One factor of that was the die size: at 200 mm2, one would have expected AMD to definitely use eight cores. For sub 125 mm2, in order to maintain GPU performance, perhaps a quad-core design only have been suitable. However, AMD is claiming a great win here: eight Zen 2 cores, with frequencies at 1.8-4.3 GHz at 15 W, and despite fewer graphics compute units (down from 11 to 8), a higher per-compute unit performance claim of +56% means that performance is actually higher. All just shy of 150 mm2.

We are living in the future. I can’t wait for more.

It's worth noting that AMD's official number for the Zen 2 die size is 74 mm2. This is derived from the floorplan of the chip, which during manufacturing has additional space added to ensure clean die seperation between adjacent die prints. Ultimately what we get as the consumer is that seperation lane (known as a scribe lane) from one side of the die to the other, which is just slightly bigger than the floor plan that AMD supplies to the fabrication plant / TSMC. With calipers, what we get is that additional space, which is above AMD's quoted size.

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  • Smell This - Monday, July 20, 2020 - link

    *** G O N D A L F ***
  • Smell This - Monday, July 20, 2020 - link

    G O N D A L F x x
  • Smell This - Monday, July 20, 2020 - link

    G O N D A L F
  • JasonMZW20 - Tuesday, January 14, 2020 - link

    Just L3 though, AFAIK. 4MB per CCX, so 4+4MB in 4800U or 1MB per core.

    Saves quite a bit of die (and power) from 16MB per CCX, but savings was, of course, reapportioned to iGPU.

    Though this is AMD's first Zen 2 design with 7nm integrated SoC silicon (DDR4/LPDDR4 PHYs and controllers included). I really want to see the die shot.
  • CrystalCowboy - Tuesday, January 14, 2020 - link

    So Renoir is all on one piece of silicon? Assume 75 mm2 for the Zen cores, that means the remaining ~75 mm2 contains not only the graphic cores but also the I/O that is on a separate piece of silicon in the Ryzen 3000 CPUs. And that I/O presumably gets a shrink so that it is all done with 7nm.
  • Ian Cutress - Tuesday, January 14, 2020 - link

    Yes, it's monolithic. The cores are less than 75, because there's less L3 cache in Renoir than a standard 8-core Zen 2 chiplet.
  • Fataliity - Tuesday, January 14, 2020 - link

    Judging by your own measurements, the Zen2 core on the APU should be about 50mm.

    You stated at release that the L3 cache was 50% of die size of the 75mm. The other 50% was the Zen2 cores. So 37.5mm die, 37.5mm L3. That was for 32MB, so at 8MB that's 1/4, or a little less than 10mm. So about 47.5mm.
  • neblogai - Tuesday, January 14, 2020 - link

    It should be roughly 50mm for cores, the rest shared in half between CUs and everything else. That is because in 75mm^2 Matisse Zen2 chiplet, ~40%(~30mm^2) is L3, but in Renoir- there is only a quarter of that cache. This could save >20mm^2, and some space on Zen2 chiplet are IF links, not cores.
  • ET - Tuesday, January 14, 2020 - link

    I'd estimate about 50 mm2 for the Zen cores with the smaller cache. I'd give the Vega cores half of that, but with the codecs and display engine possibly another 40-50 mm2 together. The rest going mainly to internal and external I/O.

    Would be interesting to see a die image when the chip arrives.
  • Kevin G - Tuesday, January 14, 2020 - link

    I was half expecting this generation of mobile chip to start following AMD's chiplet strategy via leveraging the same Zen 2 chiplets but with a IO die that had an integrated GPU. In fact, I would have thought that the IO die was also going to pull double duty as a lowend discrete GPU die when given a higher power budget.

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