Back in November last year, we reported that SK Hynix had developed and deployed its first DDR5 DRAM. Fast forward to the present, and we also know SK Hynix has recently been working on its DDR5-6400 DRAM, but today the company has showcased that it has plans to offer up to DDR5-8400, with on-die ECC, and an operating voltage of just 1.1 Volts.

WIth CPU core counts rising with the fierce battle ongoing between Intel and AMD in the desktop, professional, and now mobile markets, the demand to increase throughput performance is high on the agenda. Memory bandwidth by comparison has not been increasing as much, and at some level the beast needs to be fed. Announcing more technical details on its official website, SK Hynix has been working diligently on perfecting its DDR5 chips with capacity for up to 64 Gb per chip.

SK Hynix had previously been working on its DDR5-6400 DRAM, which has 16 Gb which is formed of 32 banks, with 8 bank groups, with double the available bandwidth and access potential when compared with DDR4-3200 memory. For reference, DDR4 uses 16 banks with 4 bank groups. The key solution to improve access throughout is the burst length, which has been doubled to 16 when compared with 8 on DDR4. Another element to consider is DDR4 can't by proxy run operations while it's refreshing. DDR5 is using SBRF (same bank refresh function) which allows the system the ability to use other banks while one is refreshing, which in theory improves memory access availability.

As we've already mentioned, SK Hynix already has DDR5-6400 in its sights which are built upon its second-generation 10nm class fabrication node. SK Hynix has now listed that it plans to develop up to DDR5-8400. Similar in methodology to its DDR5-6400 DRAM, DDR5-8400 requires much more forethought and application. What's interesting about SK Hynix's DDR5-8400 is the jump in memory banks, with DDR5-8400 using 32 banks, with 8 bank groups.

Not just content at increasing overall memory bandwidth and access performance over DDR4, the new DDR5 will run with an operating voltage of 1.1 V. This marks a 9% reduction versus DDR4's operating voltage which is designed to make DDR5 more power-efficient, with SK Hynix reporting that it aims to reduce power consumption per bandwidth by over 20% over DDR4.

To improve performance and increase reliability in server scenarios, DDR5-8400 will use on-die ECC (Error Correction) and ECS (Error Check and Scrub) which is a milestone in the production of DDR5. This is expected to reduce overall costs, with ECS recording any defects present and sends the error count to the host. This is designed to improve transparency with the aim of providing enhanced reliability and serviceability within a server system. Also integrated into the design of the DDR5-8400 DRAM is Decision Feedback Equalization (DFE), which is designed to eliminate reflective noise when running at high speeds. SK Hynix notes that this increases the speed per pin by a large amount.

In the above image from specification comparison between DDR4 and DDR5 from SK Hynix, one interesting thing to note is that it mentions DRAM chips with density up to 64 gigabit. We already know that the chip size of DDR5 is 65.22mm², with a data rate of 6.4 Gbps per pin, and uses its 1y-nm 4-metal DRAM manufacturing process. It is worth pointing out that the DDR5-5200 RDIMM we reported on back in November 18, uses 16 Gb DRAM chips, with further scope to 32 Gb reported. SK Hynix aims to double this to 64 Gb chips which do double the density, at lower power with 1.1 volts.  

Head of DRAM Product Planning at SK Hynix, Sungsoo Ryu stated that:

"In the 4th Industrial Revolution, which is represented by 5G, autonomous vehicle, AI, augmented reality (AR), virtual reality (VR), big data, and other applications, DDR5 DRAM can be utilized for next-gen high-performance computing and AI-based data analysis".

SK Hynix if still on schedule with the current Coronavirus COVID-19 pandemic, looks set to enter mass production of DDR5 later this year.

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Source: SK Hynix

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  • mode_13h - Sunday, April 5, 2020 - link

    Thanks for posting. Here are some benchmarks I found for DDR4:

    Weirdly, the dual-ECC often edges out the dual non-ECC, even though they allegedly have the same timings. Interestingly, the quad-channel config only helps in a minority of benchmarks, even on a 10-core @ 3.1 GHz CPU. However, note that the CPU is Haswell-EP, and this could be a artifact of its core topology or the sophistication of its DDR4 controller.
  • willis936 - Sunday, April 5, 2020 - link

    Here are memory scaling tests for the scenario I described (12 core 4 GHz CPU with dual channel DDR4). The difference between 2400 and 3200 is up to 10% in many applications, and that isn’t even testing for the increased latency from ECC.
  • mode_13h - Monday, April 6, 2020 - link

    The link in the post above didn't measure any increased latency from ECC vs. non-ECC (both unbuffered). Moreover, ECC RAM is currently available in speeds as high a DDR4-3200.
  • willis936 - Monday, April 6, 2020 - link

    Your response does not make any sense. I explicitly stated “that isn’t even testing for the increased latency from ECC” and then you repeat that statement in other words. That doesn’t refute the performance difference between DDR4-2400 and DDR4-3200. I would expect higher latencies to make the performance difference larger and in other applications. Non-ECC DDR4 is available in up to DDR4-5000. Your point can’t be that DDR4 ECC is twice the cost and half the speed of DDR4 non-ECC, since that’s a fact.
  • mode_13h - Tuesday, April 7, 2020 - link

    > I explicitly stated “that isn’t even testing for the increased latency from ECC”

    Your statement presumes there is some increase in latency to be measured.

    Now, the point of confusion seems to be that I was referring to the link in the post above yours, not the link in your post, which was above mine. So, to eliminate all potential for confusion, check this link, and note that they found zero difference in latency between the dual-channel ECC and non-ECC setups:

    > That doesn’t refute the performance difference between DDR4-2400 and DDR4-3200.

    It wasn't meant to. My point about ECC being available at up to DDR4-3200 was a separate point, but I'll concede that I've only found registered memory at those speeds.

    > since that’s a fact.

    Not one supported by any evidence you've so far provided.

    ECC isn't intrinsically slower. It's just that the market for ECC memory doesn't *want* DDR4-5000, because it's too expensive, power-hungry, and/or error-prone.
  • willis936 - Tuesday, April 7, 2020 - link

    I agree with your conclusion. At the end of the day, someone still has to put up a lot more money for equivalent performance ECC memory compared to non-ECC. So someone making a system needs to evaluate how much ECC is worth and how much performance is worth in their application.
  • mode_13h - Tuesday, April 7, 2020 - link

    Thanks for the follow-up. I'm glad that we could converge on a position.
  • mode_13h - Sunday, April 5, 2020 - link

    Why should ECC be half the speed of non-ECC? I don't follow this, at all. The underlying RAM is the same, other than the number of dies. So, ECC just means more data lines to the CPU and that its memory controller needs to to check/correct each "word".

    I just don't believe that last part is such a bottleneck. CPU caches often have ECC, as well, and they run much higher throughputs.
  • willis936 - Sunday, April 5, 2020 - link

    Who’s saying it has to be? I said that it is. Ask the vendors. They’ll likely tel you it’s to keep SER low, and they’d be right.
  • mode_13h - Monday, April 6, 2020 - link

    You stated "half the speed" and now you seem to be backing away from that. It seems your only case against the speed of ECC was simply that vendors don't offer it in such high speeds and low-latencies as *gaming* RAM, as if that were any kind of surprise.

    I'm currently seeing a number of options for Registered DDR4-3200 and Unbuffered DDR4-2666.

    In the context of 4-, 6-, and 8- channel memory configurations, this supposed speed penalty of ECC is a non-issue.

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