OpenCL Programming Model and Suitability for FPGAs

OpenCL is an open-standard programming interface developed by the Khronos group designed particularly for parallel and heterogeneous computing.  OpenCL can be used to program various types of hardware including CPUs, GPGPUs, FPGAs and many-core coprocessors like Xeon Phi or Adapteva's Epiphany.  Each hardware vendor that wants its hardware to be exposed to OpenCL needs to provide an OpenCL driver for its hardware. For example, OpenCL drivers are available for various CPUs and GPUs for Windows, Linux and Mac and Altera is now providing OpenCL drivers and associated development tools for their FPGAs.  Prior to OpenCL, there were no standard programming languages that exposed coprocessors on an equal footing. Thanks to the rise of GPGPU, the idea of accelerators and coprocessors has entered the mainstream and having a standard interface to accelerators is a big win for FPGA vendors.  In many ways, the concepts that apply to programming a discrete GPGPU placed on a PCIe board also apply to FPGAs.

We go over some OpenCL terminology.

Host and devices: The CPU is called the host, and each hardware that has an OpenCL driver is called a device.  Each device can have one or more compute units and each compute unit can have multiple processing element.  This is shown visually below (figure from Hands on OpenCL course).  

For example, Nvidia Titan GPU contains 15 SMX units and each SMX unit corresponds to a compute unit in OpenCL and each SMX has 192 processing elements.  On FPGAs, the number and complexity of each compute unit is not fixed and instead is customized to your application.

Unlike say C, C++, Java or Python, OpenCL cannot be used standalone. Instead, the main program runs on the CPU (the host) as usual and typically only the computationally intensive parts of the program are written in OpenCL and called from the main program.  However, work is not automatically distributed across various devices. Instead, the application program can query the OpenCL runtime for the list of all OpenCL compatible devices in a system and can choose the appropriate device for each computation. 

Device memory:  Each device has its own memory space where it can allocate arrays of data (called buffers) that can be read/written from OpenCL programs. In a discrete GPU or an FPGA, the buffer objects will typically reside in the RAM placed on the PCIe based board that contains the GPU or FPGA chip. For example, in a GPU such as Radeon 7970, the buffer objects will typically be placed in the GDDR5 RAM. OpenCL provides functions to copy data between host (CPU) memory and device memory. Some vendors also allow transferring data between multiple devices in a system directly without CPU intervention.

Kernels:  OpenCL programs consist of kernels, which are similar to functions in C. Kernels can read/write from buffer objects that are passed as arguments to the kernel. Kernels are written in a C-like programming language. The OpenCL driver for a given hardware compiles it to the appropriate format. For CPUs and GPUs, the vendor's OpenCL driver will compile it to the native instruction set of the processor.  We will get into how kernels are compiled by Altera's SDK in the next section.

Work-items, work-groups and parallelism: Unlike say C, where usually a function call leads to execution of a single instance of a function, the host launches the kernels across a 1D, 2D or 3D grid of "work-items". Each work-item can be thought of a conceptual thread and each work-item executes the same kernel function. However, each work-item knows its index in the thread and will typically compute different parts of a solution.

For example, let us say you wanted to add two vectors of length N.  This is how you will do it in plain C:

You can write a kernel where each work-item adds one element of the vector corresponding to its index. Here is the sample OpenCL kernel.

In this case, each work-item is performing the work done by one loop iteration in the C code. Thus, if you wanted to add vectors of size 1000, you will launch this kernel with 1000 parallel work-items. OpenCL is an inherently parallel API and particularly suited for highly parallel problems.

Work-items are organized into work-groups, which are small grids of say 8x8 work-items,  and items within a work-group can synchronize with each other but items from different work-groups cannot. This work-item and work-group organization maps particularly well to GPUs. FPGAs also prefer highly parallel workloads but the way they get compiled to FPGAs is very different and we will get to that soon.


Local memory:  Accessing memory is an expensive operation. CPUs include hardware-managed caches with the hope that the data that is reused in the program can be brought into the cache once and then read/written multiple times from the cache. However, some architectures such as all recent desktop GPUs from AMD, Nvidia and Intel include small amount of fast memory on-chip that acts as a software managed cache. OpenCL provides a construct called "local memory" to expose such software managed caches. Each work-group can allocate local memory (typically upto 32 or 64kB per work-group) and all work-items in the work-group can read/write from the local memory. Local memory is implemented via the software managed cache on GPUs while CPUs allocate it in regular RAM and hope that it will be end up in the cache during program execution. FPGAs also include on-chip memory that can be used to implement OpenCL's local memory construct in hardware. Some members of the Stratix V series include upto 52Mbit (~6.5MB) of on-chip memory that can be used as local memory. In comparison, Radeon HD 7970 includes about 2MB of local memory on-chip and a GTX Titan includes about 450kB of local memory.

You can learn more about OpenCL at the official page at Khronos or look over some tutorials such as the recently released Hands on OpenCL. Overall, the OpenCL programming model looks to be a surprisingly good fit for FPGAs. Concepts such as host/device separation, device memory vs CPU memory, inherently parallel programming model and finally the local memory abstraction all look to be very well suited to FPGAs.

Introduction: FPGAs and Altera's Products Altera's OpenCL Implementation Details
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  • ShieTar - Thursday, October 10, 2013 - link

    Altera is offering FPGAs in 4 different general speed-grades, which define a maximum clock frequency (between 525 and ~800 MHz). The actual frequency of the completed design will depend on the complexity of the design, and can sometimes be restricted to little more than half the maximum clock frequency.

    Of course the end-user can always decide to run at a lower performance, specifically if he has a input or output with a fixed data rate. Have a look at the data sheets if you want more detailed information on this topic:
  • John32 - Thursday, October 10, 2013 - link

    Yes, I'm aware of speed grades and the "up to" frequencies of FPGAs. My point is that writing OpenCL code for the FPGA won't be as transparent as programmers would like for it to be worth while. They'd need to consider how their code will translate to hardware no matter how good Altera claims their compiler is. This would result in applications that would run well on FPGAs but not necessarily well on traditional devices.

    Also, I'm sure people won't like that one revision of their application runs at 300 MHz while another runs at 100 MHz or doesn't fit into the FPGA. Being non-digital designers, they won't know why.

    It seems the applications this will benefit from will be fairly limted in scope.
  • kirsch - Thursday, October 10, 2013 - link

    > However, programming FPGAs has traditionally been difficult and requires expertise
    > in specialized "hardware description languages" (HDLs) like VHDL or Verilog.

    Another notable option is National Instruments LabVIEW FPGA product. It allows programming in G, LabVIEW's relatively easy-to-use graphical programming language, and deploy to an FPGA where code runs extremely fast and can leverage the inherent parallelism of the hardware.
  • rahulgarg - Thursday, October 10, 2013 - link

    Thanks! Noted! Not being from a traditional FPGA background, I missed that somehow. If we do followup posts, will investigate LabVIEW as well.
  • alxx - Sunday, October 13, 2013 - link

    problem with labview is the second you go commercial the costs/royalties add up like nothing else
  • Rob94hawk - Saturday, October 12, 2013 - link

    I have no idea what it does but it sure does look cool.
  • ghulands - Saturday, October 12, 2013 - link

    There was a video I watched on youtube from the x264 devs talking about which algorithms they ported to open cl -
  • alxx - Sunday, October 13, 2013 - link

    See if you can get your hands on one of either xilinx zedboard or parallela board - both have a zynq chip (dual hardcore arm Cortex 9 + fpga) so can run android or linux with the fpga to provide custom peripherals. Parallela board has adaptevas custom multicore micro which can be programmed with opencl

    opencl on parallela (ephiany processor not fpga)

    Waiting for my parallella board to turn up.

    Xilinx provides c to fpga tools in their vivado suite and their boards are usually a lot cheaper than alteras ( has some of the cheapest fpga boards) . Though terasic provide some nice altera based boards.
  • alxx - Sunday, October 13, 2013 - link

    looks like xilinx joined the opencl effort but no timeline for when they'll provide support :-(
  • moozoo - Sunday, October 13, 2013 - link

    Anyone looking at this seriously should read though all of Table 6 that starts on page 17 of the Altera SDK for OpenCL Programming Guide.

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