At Micron's 2017 Analyst Conference yesterday in Scottsdale, Arizona, Micron executives provided updates on the status and future plans for all their major business units. While no new products were announced at this investor-focused event, their projections offer some insight about what's in store for the memory industry in 2017 and beyond. With both NAND flash and DRAM in short supply globally, Micron's projections of increasing production volume and decreasing cost per bit are welcome reassurance.

NAND Flash: 64-layer 3D NAND This Year, Additional Focus on Small Die Products

In 2016, Micron and Intel's joint venture became the second manufacturer to sell 3D NAND flash in volume. That 32-layer first generation 3D NAND has reached mature yields that are comparable to that of planar NAND processes, and since last fall 3D NAND has accounted for a growing majority of Micron's NAND output on a per-bit basis.

In 2017 Micron will be ramping up production of their 64-layer second generation 3D NAND, which is currently sampling. They promise "meaningful output" by the end of their fiscal year (December 2017). The 64-layer 3D NAND will increase the total GB per wafer by more than 80% and decrease the cost per bit of TLC by at least 30%.

With the second generation 3D NAND, Micron is shifting their strategy slightly by offering at least two different die sizes. We've previously heard about the 512Gb 64-layer 3D TLC part, but Micron will also be making a smaller 256Gb 3D TLC part. This die is planned to be the smallest 256Gb NAND flash die available from any vendor, at 59 mm^2 or 4.3Gb/mm^2. The smaller die is intended for the mobile market where the 512Gb part will be physically too large. Micron's market share for NAND in the mobile market has been quite low, in part because they tend toward making large, high-capacity chips. The new smaller part will give them a chance to go after a much larger share of the rapidly expanding mobile storage market. The smaller part may also see some use in the SSD market for the smallest models in each family, to avoid the pitfalls of having too few dies to stripe data accesses across.

Micron is not ready to share many specifics of their third generation 3D NAND flash, but they plan to begin small scale manufacturing in the second half of 2017. They are estimating that GB/wafer will improve by more than 40%, suggesting that they'll be moving to about 96 layers. They have not yet projected what cost per GB savings can be expected with the third generation 3D NAND.

Four bit per cell (QLC) NAND flash is also something Micron has worked on, but they do not yet have speficic plans for introducing it as a product. They are watching the demand quite closely and plan to be ready to introduce QLC NAND for certain cloud computing uses once the market is ready. (The very low write endurance of QLC NAND makes it necessary for software to be modified to minimize unnecessary writes, and QLC drives will generally not be suitable as drop-in replacement of 3D TLC NAND.)

DRAM: Sub-20nm This Year, GDDR6 Getting Closer

Last year, Micron ramped up production of their 20nm DRAM, and by the third quarter 20nm was a majority of Micron's DRAM output. In 2017, Micron will be ramping up and begin transitioning to their "1x nm" (16nm) node for DRAM, improving cost per GB by at least 20%. They plan to introduce 16nm GDDR5 later this year. Development is underway for both their 1Y nm and 1Z nm DRAM nodes, with initial manufacturing of 1Y nm DRAM expected to begin in the second half of 2017. Overall, they estimate the 1Y nm node is about a year behind the 1X nm node. GDDR5X volume is expected to grow significantly to satisfy bandwidth-hungry uses involving GPUs and networking, and around the end of this year or early next year Micron plans to introduce GDDR6 memory.

Other Memory Technologies: Still Quiet on 3D XPoint

As usual, relatively little was said about 3D XPoint. Micron considers the memory to be "commercially ready" technology, with work underway on second and third generation 3D XPoint chips. The new generations will bring significant performance and density increases, but there are no numbers to back up those statements yet.

No specific products have been announced under their QuantX brand for 3D XPoint, but Micron plans to have some early market adoption of 3D XPoint by the end of the year. Even once 3D XPoint-based NVDIMMs are available, Micron is not concerned that 3D XPoint will significantly cannibalize their DRAM or NAND business.

Separate from 3D XPoint, Micron is working on at least one other new memory technology, as an in-house project instead of a collaboration with Intel. This new technology has not been named by Micron, but it will apparently allow for DRAM-like performance, which would be significantly higher than what 3D XPoint can deliver. This unspecified technology also has a clear potential for cost scaling, perhaps through increasing layering. The target it to be a bit slower and cheaper than DRAM, taking into account where DRAM technology is expected to be by the time this new memory comes to market. This is not at all an imminent revolution, and it could be a decade before it is mass produced and getting used in mainstream situations.

Trends: NAND Market Grows, EUV Slips Again

As for long-term trends, Micron sees the memory market as a whole becoming less volatile as DRAM's boom and bust cycles get less severe and NAND flash with its steadier growth accounts for an ever increasing share of the memory market. Weathering periods of oversupply and their associated price crashes is trying for memory manufacturers, and usually requires significant cuts to capital expenditures, which can delay the introduction of new technologies.

In spite of current shortages, Micron expects healthy growth in volume and decrease in cost per bit for both DRAM and NAND over the next few years. NAND flash sales are expected to grow faster than DRAM, so while DRAM is currently a larger part of Micron's business than NAND flash, that may change in a few years. Micron expects the memory market as a whole to grow at about 2.5 times the growth rate of the rest of the semiconductor industry.

In general, Micron is not looking to become significantly more vertically integrated. In particular, they do not want to become a competitor to their valuable DRAM customers. However, Micron is pursuing innovations in packaging, and they want to significantly expand their market share for what they call heterogeneous multi-chip packaging (xMCP): putting DRAM, NAND and logic in one package, such as for mobile devices or BGA SSDs.

Meanwhile it will surprise absolutely nobody to hear that Micron's deployment of extreme ultraviolet (EUV) lithography has experienced a setback. Last spring Micron reported that they planned to have their first EUV tool installed in their research fab by the end of the year. The equipment is in place but not online yet, so Micron does not yet have any preliminary results to report. Micron says nothing on their current roadmaps requires EUV, so at this point it is just a potential for cheaper or more efficient manufacturing, not a looming roadblock.

Finally, after three decades with Micron and having spent the past five years as its CEO, Mark Durcan has announced his intention to retire as soon as the board of directors can hire a successor. Durcan had previously announced plans to retire in 2012 while serving as the company's president, but the death of then-CEO Steve Appleton prompted Durcan to postpone his retirement indefinitely to serve as Micron's CEO. A new CEO could be found in a matter of weeks or the search may take months; either way, Durcan plans to stick around to ensure a smooth transition.

Source: Micron

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  • SaolDan - Friday, February 3, 2017 - link

  • close - Friday, February 3, 2017 - link


    Is GDDR6 the successor of GDDR5 or GDDR5X? Seeing how the former is DDR and the latter is actually QDR I would have thought they'll also change the name.
  • Billy Tallis - Friday, February 3, 2017 - link

    They described GDDR6 as an evolution of GDDR5x.
  • close - Monday, February 13, 2017 - link

    GDDR5X is not DDR, it's QDR.
  • ddriver - Friday, February 3, 2017 - link

    Unfortunately reliability and endurance drop faster than the cost. I for one am not too keen on lower process node nand. I'd rather have them keep stacking it up, preferably in some ancient process, like 40 nm or so. Plenty of old fabs that can keep churning chips. Silicone itself is neither expressive nor rare.
  • ddriver - Friday, February 3, 2017 - link

    *silicon, not silicone lol
  • edzieba - Friday, February 3, 2017 - link

    What on earth happened to Hybrid Memory Cube? Intel and Micron were both partners on its development, but Micron basically doesn't even mention it anymore, and the only Intel product I can think of that is even slated to use it is Knights Landing.
  • Yojimbo - Friday, February 3, 2017 - link

    Last year at Hot Chips Micron included HMC in their presentations and someone from Micron called HBM a poor-man's HMC, or some words to those effects, if I recall.

    It looks to me like all TSV memory has penetrated the market much less than what people were previously saying. A couple of months ago I was wondering what happened to Wide IO, because I haven't heard anything about it. HBM has been used but only sparingly. I think it's just been too expensive to make thus far.
  • ZeDestructor - Friday, February 3, 2017 - link

    From the performance of Fury and P100, and comparing to 3DS DDR4 it looks like the interposer is the really hard part for HMC/HBM. Most likely Intel is keeping HMC for the top-tier stuff, the big Xeons on the Purley platform and Xeon Phi.
  • patrickjp93 - Friday, February 3, 2017 - link

    It's being used in enterprise. Intel uses it on Xeon Phi. There's a specialized variant of the Stratix X coming which uses it. Fujitsu makes Sparc CPUs attached to HMC. And IBM has a few specialized machines which use it too. It's just not a JEDEC standard, so it's not coming to consumerville any time soon.

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