QNAP TS-x51 NAS Series: Intel Quick Sync Gets its Killer Appby Ganesh T S on June 22, 2014 6:45 PM EST
QNAP Goes Bay Trail
Intel's Bay Trail-D takes the original Bay Trail configuration pretty much as-is. One of Intel's marketing slides for Bay Trail-D (and -M) is reproduced below for aiding our analysis.
Despite not being specifically mentioned, we know there are two SATA II (3 Gbps) ports in Bay Trail-D from the previous section. Combined with the four PCIe 2.0 lanes, the configuration is pretty much similar to the Atom D2700 along with a NM10 chipset in terms of I/O. The advantage is that all the high-speed I/Os come direct from the SoC and are not bottlenecked by DMI lanes, and the PCIe revision is 2.0 instead of 1.0. In addition, we also have a USB 3.0 port.
The Celeron J1800 used in the TS-x51 is a 2C/2T solution with a base frequency of 2.41 GHz and a burst speed of 2.58 GHz. With a 10W TDP, it is amenable to passive cooling with the appropriate chassis, but, in a NAS like the x51, it is a moot point since the drives require cooling anyway. The TS-x51 series comes in 2,4,6 and 8-bay varieties and all of them come with two GbE ports. While the 2 and 4-bay varieties come with 2x USB 3.0 ports, the 6 and 8-bay ones come with 3x USB 3.0 ports. Based on the above information, we can infer the following distribution of the high-speed interfaces amongst the various I/Os.
|QNAP TS-x51 Series High-Speed I/O Usage [ UPDATED ]|
|PCIe 2.0 x1||GbE Port 1||GbE Port 1||GbE Port 1||GbE Port 1|
|PCIe 2.0 x1||GbE Port 2||GbE Port 2||GbE Port 2||GbE Port 2|
|USB 3.0 x1||2x USB 3.0 (Hub)||2x USB 3.0 (Hub)||3x USB 3.0 (Hub)||3x USB 3.0 (Hub)|
|PCIe 2.0 x2||Free for Drive Bays|
|SATA II x2|
While the 2-bay unit is capable of having probably all I/Os accessible through the SoC fabric at full speeds, the 4-,6- and 8-bay varieties need some trade-offs. [Update: QNAP confirmed that they are using a USB 3.0 hub chip as one of the commenters pointed out]. In the above table, we see that two PCIe 2.0 lanes and two SATA II (3 Gbps) lanes are available for connecting all the drives in the bays to the SoC. In the absence of a I/O Controller Hub (that made the previous generations of Atom-based NAS units simple to design), each vendor is now free to choose between a number of different available options.
An issue with the Celeron J1800 (and Bay Trail-D in general) is that the SATA ports don't support port multipliers. In addition, there is only one SATA controller behind the two SATA ports. This places undue stress on the two free PCIe link to service a large number of bays. Our educated guess is that QNAP uses a number of PCIe to SATA bridges (such as the Marvell 88SE9130 and the ASMedia ASM1061 for PCIe x1 to 2x SATA and Marvell 88SE9215 for PCIe x1 to 4x SATA).
This still doesn't explain how the TS-851 is configured (I am yet to see a PCIe x1 to 6x SATA bridge chip). It will be interesting to see the break-up, but, at this moment, QNAP has not got back with answers to our clarification requests. The addition of two USB 3.0 ports to the 6- and 8-bay models actually takes away a PCIe x1 lane that could have otherwise been used for the drive bays. I am not sure how many users need more than one USB 3.0 slot in a NAS.
Update: QNAP came forward with clarifications on the I/O distribution:
- TS-251: 1x ASM1061 (i.e, two SATA ports are served by one PCIe link)
- TS-451: 2x ASM1061 (four SATA ports from two PCIe links)
- TS-651: 2x 88SE9215 (three SATA ports per PCIe link)
- TS-851: 2x 88SE9215 (four SATA ports per PCIe link)
Coming back to the Celeron J1800 SoC, the two features most relevant to us in this piece are the availability of Quick Sync (something not claimed in the initial Bay Trail launch) and VT-x (support for virtualization). We will be covering this in the next two sections. Prior to that, a quick note on the J1800 which has both 2013 B3 as well as 2014 C0 steppings. Intel started playing up the Quick Sync capabilities of the Bay Trail-D / Bay Trail-M parts for products which are part of the push for the 'Back-to-School 2014' season.
It appears from the above slide that only the 2014 C0 steppings of the J1800 have QuickSync enabled (we are still waiting for confirmation from Intel on this). Since the hardware accelerated transcoding features of the TS-x51 are dependent on Quick Sync, it is obvious that the TS-x51 must be using the C0 stepping of the Celeron J1800.