Samsung and TSMC made several important announcements about the present and future of their semiconductor manufacturing technologies in March. Samsung revealed that it had shipped over 70 thousand wafers processed using its first-generation 10 nm FinFET fabrication process (10LPE) and also announced major additions to its upcoming manufacturing technology roadmap. In particular, the company plans to introduce three processes it has not talked about thus far. TSMC said that it is about to start mass production of ICs (integrated circuits) using its first-gen 10 nm technology and also announced several new processes that will be launched in the coming years, including its first 7 nm EUV process due in 2019.

10 nm: Samsung Is Shipping

Update 5/12: Samsung informed us that its press release from October, 2016, compares characteristics of the 10LPE manufacturing technology with those of the 14LPE, not 14LPP. The text and table have been updated accordingly.

Samsung said it had started to make SoCs using its 10LPE fabrication technology last October, which is something we already knew. This manufacturing process allowed the company to make its chips 30% smaller compared to ICs made using its 14LPE process as well as reducing power consumption by 40% (at the same frequency and complexity) or increase their frequency by 27% (at the same power and complexity). So far, Samsung has processed over 70 thousand wafers using its 10LPE technology, which can give an idea about Samsung’s 10 nm production capacities (considering that the whole 10 nm production cycle is greater than the 90 days we saw with previous-gen FinFET processes). At the same time, keep in mind that Samsung does not have many 10 nm designs to manufacture right now: we know only of the company’s own Exynos 9 Octa 8895 as well as Qualcomm’s Snapdragon 835 seen in the Samsung Galaxy S8.

Advertised PPA Improvements of New Process Technologies
Data announced by companies during conference calls, press briefings and in press releases
  GF Samsung
7nm DUV
vs 14LPP
vs 28LPP
vs 14LPE
vs 14LPP
vs 10LPE
Power >60% 60% 40% 30% ~15% ?
Performance >30% 40% 27% >10% ~10% ?
Area Reduction >50% 50% 30% 30% none ?

In addition to its production milestone, Samsung also confirmed plans to start mass production of chips using its second-generation 10 nm manufacturing process called 10LPP (10 nm low-power plus) by the end of 2017 as well as its third-generation 10 nm technology called 10LPU by the end of 2018. Samsung said last year that the 10LPP is going to enable a ~10% performance increase (at the same power and at the same complexity) versus the 10LPE, but we know absolutely nothing about the 10LPU. It is logical to assume that the 10LPU will bring certain PPA-related (performance, power, area) improvements, but it is not clear how Samsung plans to achieve them and which one of the three will be the focus for improvements. As it appears, just like Intel, Samsung has ended up with three generations of 14 nm fabrication processes and is going to end up with three generations of 10 nm manufacturing technologies. It is noteworthy that Samsung itself does not use its 14LPC (low-power compact) for its leading edge SoCs, which may suggest that the 10LPU is also not aimed at this segment of the market. In fact, it is highly likely that the 10LPU will target ultra-small and ultra-low-power ICs for various emerging devices, but Samsung yet has to confirm that.

10nm: TSMC Is Steady

As for TSMC, its 10 nm process technology (CLN10FF) is now qualified for production at the company’s GigaFabs 12 and 15, where high-volume ramp is expected to start in H2 2017. Production capacity of these two fabs is hundreds of thousands wafer starts per quarter and TSMC plans to ship 400 thousand wafers processed using its 10 nm manufacturing tech this year. Considering the long production cycles for FinFET-based technologies, it is about time for TSMC to start ramping up 10 nm so to be able to supply enough chips to its main customer in time. Apple is expected to launch its new iPhone products in September or October and needs to get SoCs couple of months before the launch.

Advertised PPA Improvements of New Process Technologies
Data announced by companies during conference calls, press briefings and in press releases
Power 70% 60% 40% 60% <40%
Performance 65% 40% 20% 30% ?
Area Reduction ~50% none >50% 70% >37%

PPA advantages of TSMC’s CLN10FF over its CLN16FF+ (second-gen 16 nm) have been discussed already and they are significant for developers of mobile SoCs (but not that significant for makers of other ICs): a ~50% higher transistor density, a 20% performance improvement at the same power and complexity or a 40% lower power consumption at the same frequency and complexity. Unlike Samsung, TSMC does not seem to plan multiple generations of 10 nm and will go straight to 7 nm next year. 7nm is currently very popular among chip designers, indicating a future major milestone. However, in addition to the CLN7FF, the company will also offer several other manufacturing technologies for ultra-small and ultra-low-power applications.

Beyond 10 nm at TSMC: 7 nm DUV and 7 nm EUV
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  • Meteor2 - Sunday, May 7, 2017 - link

    Do you mean Broadwell? But what's OC'd clock speed got to do with anything?
  • jjj - Friday, May 5, 2017 - link

    Pretty sure that the 10nm LPE perf claims are vs 14LPE not LPP as 27% higher perf is way too much.
  • Anton Shilov - Friday, May 5, 2017 - link

    Regarding the 10LPE vs 14LP*, I am not sure because we have two statements that contradict each other from Samsung.

    They stated the following in October:

    "Samsung’s new 10nm FinFET process (10LPE) adopts an advanced 3D transistor structure with additional enhancements in both process technology and design enablement compared to its 14nm predecessor, allowing up to 30-percent increase in area efficiency with 27-percent higher performance or 40-percent lower power consumption."

    But if you look at the picture (from August) there (, they mentioned ~30% performance increase at the same leakage power, which can considered as 27%... But if you happen to see some more up to date slides from Samsung, please let me know.
  • jjj - Saturday, May 6, 2017 - link

    If they had anywhere close to 27% over 14LPP , they would have more design wins so it's safer to assume that "predecessor" means LPE. The phrasing itself is iffy, why "compared to ïts 14nm predecessor" and not just "compared to 14nm" - corporations are tricky like that.
  • jjj - Sunday, May 7, 2017 - link

    Hong Hao, senior vice president of the foundry business at Samsung Semiconductor "10nm brings a lot of benefits to our customers in terms of area scaling, performance and power or PPA. So overall, the PPA improvements are very substantial compared 14nm. We have compared that in terms of the performance, area and power to 14nm LPE. 14nm LPE is our first-generation finFET technology. We see up to a 30% area reduction with a 27% performance improvement or 40% lower power at the same performance."
  • willis936 - Friday, May 5, 2017 - link

    Feynman is crying tears of joy in his grave. Intel is crying for another reason.
  • melgross - Friday, May 5, 2017 - link

    Oh, I don't know. It's acknowledged that Intel's current 14nm process is equivelant to other's 10nm processes, and likely their 10nm will be equivelant to other's 7nm.

    I don't think Intel has anything to,worry about for the next few years. I still doubt that 5nm will come about, at least, not as a real 5nm process, though it will likely be advertised as such.

    But when that wall is reached, for everyone, then, long last, Intel will lose most of its process advantages. But that will be in 5 to 8 years, so there's still a long way to,go.
  • tarqsharq - Friday, May 5, 2017 - link

    We'll have to see if we get another materials switch up off silicon.

    Some kind of graphene, maybe a photon based solution instead of electron?

    Apparently quantum computing is only useful for certain types of operations, so that's not a magic bullet for speeding up all of our computing tasks.
  • Meteor2 - Friday, May 5, 2017 - link

    I reckon we'll get real 5 nm, probably with quad patterning, possibly with a new transistor design, in around 2023-25. Difficult to see where we can go after that. Maybe that graphene stuff I suppose.
  • vladx - Friday, May 5, 2017 - link

    Nanotubes seems the most feasible solution.

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