PCI-SIG Finalizes PCIe 5.0 Specification: x16 Slots to Reach 64GB/sec
by Ryan Smith on May 29, 2019 6:30 PM ESTFollowing the long gap after the release of PCI Express 3.0 in 2010, the PCI Special Interest Group (PCI-SIG) set about a plan to speed up the development and release of successive PCIe standards. Following this plan, in late 2017 the group released PCIe 4.0, which doubled PCIe 3.0’s bandwidth. Now less than two years after PCIe 4.0 – and with the first hardware for that standard just landing now – the group is back again with the release of the PCIe 5.0 specification, which once again doubles the amount of bandwidth available over a PCI Express link.
Built on top of the PCIe 4.0 standard, the PCIe 5.0 standard is a relatively straightforward extension of 4.0. The latest standard doubles the transfer rate once again, which now reaches 32 GigaTransfers/second. Which, for practical purposes, means PCIe slots can now reach anywhere between ~4GB/sec for a x1 slot up to ~64GB/sec for a x16 slot. For comparison’s sake, 4GB/sec is as much bandwidth as a PCIe 1.0 x16 slot, so over the last decade and a half, the number of lanes required to deliver that kind of bandwidth has been cut to 1/16th the original amount.
The fastest standard on the PCI-SIG roadmap for now, PCIe 5.0’s higher transfer rates will allow vendors to rebalance future designs between total bandwidth and simplicity by working with fewer lanes. High-bandwidth applications will of course go for everything they can get with a full x16 link, while slower hardware such as 40GigE and SSDs can be implemented using fewer lanes. PCIe 5.0’s physical layer is also going to be the cornerstone of other interconnects in the future; in particular, Intel has announced that their upcoming Compute eXpress Link (CXL) cache coherent interconnect will be built on top of PCIe 5.0.
PCI Express Bandwidth (Full Duplex) |
|||||||
Slot Width | PCIe 1.0 (2003) |
PCIe 2.0 (2007) |
PCIe 3.0 (2010) |
PCIe 4.0 (2017) |
PCIe 5.0 (2019) |
||
x1 | 0.25GB/sec | 0.5GB/sec | ~1GB/sec | ~2GB/sec | ~4GB/sec | ||
x2 | 0.5GB/sec | 1GB/sec | ~2GB/sec | ~4GB/sec | ~8GB/sec | ||
x4 | 1GB/sec | 2GB/sec | ~4GB/sec | ~8GB/sec | ~16GB/sec | ||
x8 | 2GB/sec | 4GB/sec | ~8GB/sec | ~16GB/sec | ~32GB/sec | ||
x16 | 4GB/sec | 8GB/sec | ~16GB/sec | ~32GB/sec | ~64GB/sec |
Meanwhile the big question, of course, is when we can expect to see PCIe 5.0 start showing up in products. The additional complexity of PCIe 5.0’s higher signaling rate aside, even with PCIe 4.0’s protracted development period, we’re only now seeing 4.0 gear start showing up in server products; meanwhile the first consumer gear technically hasn’t started shipping yet. So even with the quick turnaround time on PCIe 5.0 development, I’m not expecting to see 5.0 show up until 2021 at the earliest – and possibly later than that depending on just what that complexity means for hardware costs.
Ultimately, the PCI-SIG’s annual developer conference is taking place in just a few weeks, on June 18th, at which point we should get some better insight as to when the SIG members expect to finish developing and start shipping their first PCIe 5.0 products.
Source: PCI-SIG
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sorten - Wednesday, May 29, 2019 - link
"too expensive" is an odd statement. If it were too expensive for AMD produce then they wouldn't produce it, because they would have performed the necessary marginal analysis. If it were going to be too expensive for consumers, then again AMD wouldn't include it.So reality is contradicting blogger speculation, I guess? *shrug*
alchemist83 - Wednesday, May 29, 2019 - link
LOL. Them bloggers be so clever. Cos they got plenty mugs to listen and take every BS sentence as gospel.alchemist83 - Wednesday, May 29, 2019 - link
Wot? Just babble.. Expensive ON AMD mobos? How so. What does that even mean? English, grammar, words, semantics. Get sum.PixyMisa - Wednesday, May 29, 2019 - link
Except that it even works on existing motherboards originally designed for PCIe 3.0.mode_13h - Wednesday, May 29, 2019 - link
Only on slots near the CPU.Also, you don't know what guidance AMD could've given board designers, with the knowledge that they'd want to enable PCIe 4.0, in the future. Remember, AMD *planned* for AM4 to last a while, so they probably had some idea PCIe 4.0 would be coming.
nevcairiel - Thursday, May 30, 2019 - link
"Works", sort of. You likely get one slot with a direct connection to the CPU doing it. For mainboards right now, the big advantage in PCIe4 is the increased bandwidth for the chipset to communicate with the CPU - and thats of course only available on new boards where the chipset speaks PCIe 4.0mode_13h - Thursday, May 30, 2019 - link
Yes, exactly.alchemist83 - Wednesday, May 29, 2019 - link
Exactly!alchemist83 - Wednesday, May 29, 2019 - link
What an odd thing to say or believe if heard. Its like claiming its been stated that DDR5 will be too expensive for the mainstream.. At what point in time are they referring?? Before its mass release to the public world then YES. PCIE 6, 7, 8, DDR 5,6,7 etc will all probably exist. And the mainstream will have access. Given time. Its how the PC business moves forward - with upgrades.Deses - Wednesday, May 29, 2019 - link
It's just basic demand and offer. When everyone moves from the old technology to the newer one and everyone mass produces it, costs go down.It's been always like that...