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  • ddriver - Monday, October 3, 2016 - link

    How can this possibly backfire?
  • Meteor2 - Monday, October 3, 2016 - link

    Are you OK?
  • ddriver - Monday, October 3, 2016 - link

    I am great, but glofo won't be when they fail to deliver and in 2019 the best they could offer is 14 nm lines.

    Intel is pretty much the leader in process, and even they don't do stupid things like going ahead of themselves, in fact they have switched process transition to a lower gear. It is highly unrealistic that glofo, the sloth of the semiconductor business, will succeed.

    That's not playing it safe, that putting all your eggs in a basket you can't deliver. Playing it safe would be baby steps, not skipping node leaps.
  • ddriver - Monday, October 3, 2016 - link

    Best case scenario IMO is that it will be more like Intel's 10 nm, but will call it 7 cuz it sounds better. That should be achievable at least.

    Let's face it, glofo's 14nm came almost 2 years late and wasn't exactly stellar as polaris efficiency has revealed.
  • Morawka - Monday, October 3, 2016 - link

    GF had working 7nm silicon over a year ago (in partnership with IBM), it's not so far fetched. Intel has fallen behind and they used to have a full 2 year lead, not so much anymore.

    I would be worried if i was a intel shareholder. Tick Tock Optimize should tell you something. They are gonna be on 10nm for the next 2-3 years
  • ddriver - Monday, October 3, 2016 - link

    It tells me that process will not scale down infinitely, ~10 years from now it will hit a brickwall.
  • Morawka - Monday, October 3, 2016 - link

    I know but my point is, if intel's gonna be on 10nm for 2 years, then GF has plenty of time to get 7nm out, even if it's late, they will be ahead by half a node, even with intel's superior fin pitch. Intel knows this, thats why they are finally willing to fab chips for fabless companies

    in 10 years when they hit a brick wall, they will simply stack more layers up and up.. Right now, only the base layer is etched at 14nm, 90% of the other layers are etched at a much bigger process to improve yields and provide electron flow. Here is a cross section of a Intel i7: http://imgur.com/a/wXWGX

    Metal interconnect is the real brick wall, thats why we are seeing material scientist experiment with new materials like Indium gallium arsenide and indium phosphide combined based devices. Silicon will eventually be abandoned in the high end, and down the chain as years go by.
  • ddriver - Tuesday, October 4, 2016 - link

    I get your point, but that doesn't' change the fact glofo are slow and their process quality is inferior, or in short - IBM or not, they are far from excelling at what they do. Thus getting ahead of themselves has a huge potential to backfire.

    Johnny boy has problems passing 9-th grade, he is being held for e year or two behind his mates. How smart it is for Johnny boy to "make up" for it by skipping ahead to the 12-th grade exam when he struggles to complete the 10-th? 12-th grade example is harder than 10-th grade.

    The most likely scenario is they will manage to pull something off, but as usual - delay it, and when it is finally out, it may perform worse than intel and samsung 10 nm and with lower density. And when they finally make chips on it, analysis will reveal that "your nm ain't the same as my nm", or, that it was just a PR number and it is in reality a decorated 10 nm process.
  • witeken - Wednesday, October 5, 2016 - link

    No, the interconnect has nothing to do with it. I don't think you understand what the interconnect is for. The interconnect simply transports the data, so only the interconnect layers just above the transistor need to be small.

    InGaAs is researched as a channel material, which is part of the transistor, not the interconnect.
  • Michael Bay - Monday, October 3, 2016 - link

    >IBM

    So we can bury it right now and save orselves the wait, huh.
  • name99 - Tuesday, October 4, 2016 - link

    Remember it's not even Tick Tock Optimize anymore.
    Now it's Tick Tock Optimize "Change the name and hope people get excited".

    Remember, on the desktop, Kaby Lake (Optimize) is being followed not by Cannonlake (Tick) but by Coffee Lake (fresh coat of paint, and all new codes numbers that now go up to 11).
  • witeken - Wednesday, October 5, 2016 - link

    They will have 3 versions of 10nm, so those could be decent improvements potentially, like their 14nm+ which is quite good.

    But that doesn't matter. Intel's process lead is not going to go away. Intel's 14nm *right now* is 1.4x denser than other companies can offer right now (predicting the future in semiconductors is really hard, so I throw this *current fact* out there).

    Intel's 10nm will be just as dense as Samsung or TSMC or Global Foundries 7nm. In terms of performance and power, it will be far superior with III-V, Ge and quantum wells.
  • StrangerGuy - Tuesday, October 4, 2016 - link

    The apple doesn't fall far from the AMD tree: Always hyping about future, never deliver on the present.
  • Agent Smith - Tuesday, October 4, 2016 - link

    This ain't about AMD, it's about chip manufacturers and the next few years ahead. Anybody who buys chips from them are affected yes, but your dig is plain lazy.

    Read the article for what it is and save your buying preferences to yourself.
  • StrangerGuy - Tuesday, October 4, 2016 - link

    So, we are supposed to believe a chip fab that has repeatedly been late in process over and over again on how they are going to beat Intel 10nm by 2H 2018. Looks exactly like the same usual hype garbage AMD has been feeding us over the years.
  • Vayra - Friday, October 7, 2016 - link

    You're a lost case.
  • Ali Husein - Friday, January 6, 2017 - link

    I would not say they are behind in terms of efficiency at all (my calculations prove that if the 1060 and the RX480 were on the same levels of efficiency, the RX480 would have a TDP of >158 watts) The RX480 has 5.8 Teraflops of compute power, while the GTX1060 has 4.4 teraflops of compute power. The RX480 has ~131.75% more compute power than the 1060, and if you multiply that by TDP of the 1060 (120 watts), the wattage adds up to just above 158 watts
  • ws3 - Monday, October 3, 2016 - link

    I really hope GF meets this schedule and is able to fab some great chips. Sadly, however, I'm not counting on it.
  • hammer256 - Monday, October 3, 2016 - link

    I know the process size that is reported shouldn't be taken too seriously, but a jump from 14nm to 7nm would traditionally represent a 4x area reduction, right? Isn't that a 2 node jump? Obviously that's assuming that the fab is using the same metric for measuring the 7nm and 14nm processes, and assuming that everything else scales accordingly, which is probably not the case. Still, the area reduction should be way higher that 50%. Of course, given how fabs report their process sizes, it's hard to tell exactly what's going on....
  • psychobriggsy - Monday, October 3, 2016 - link

    Yeah, I would just think of them as marketing names to be honest.

    They have slightly different characteristics anyway, density isn't the be-all and end-all of a process.
  • Morawka - Monday, October 3, 2016 - link

    no thats a single node drop. 10nm is a half node from 14nm
  • MrSpadge - Tuesday, October 4, 2016 - link

    No, full node shrinks scale the length by square root of two (1.4) to imrpove desnity by a factor of 2. So 14 to 10 nm is a full node, wheres 14 to 7 nm should be 2 full nodes. Otherwise it's not what people used for node classification and potentially misleading.
    Anyone can skip "10 nm" if they simply call the same thing "7 nm".
  • Morawka - Tuesday, October 4, 2016 - link

    your argument contradicts itself. First you say a full node happens when densitiy improves by a factor of 2, but then you say 14nm to 10nm is a full node, despite only increasing density by a factory of 1.4.

    Shrinking or modifying FEOL and BEOL at the same time is a full node. TSMC went from 20nm to 16nm, (ie half node or hybrid node)

    http://www.extremetech.com/computing/235842-global...
  • CiccioB - Tuesday, October 4, 2016 - link

    14 vs 10nm improves (or should improve) density with the square of the linear dimensions, that is 196 vs 100, that is a 2x increase.

    From 14 to 7 the density improvement should be 4x.

    But we already know from a lot of past PP that shrinking is not so linear with the nm associated to the PP, even less now with Finfet transistors.
  • JKflipflop98 - Thursday, October 6, 2016 - link

    "Anyone can skip "10 nm" if they simply call the same thing "7 nm"."

    That's exactly what is going on. Basically, the only company you can even halfway trust on pitch dimensions anymore is Intel. Everyone else is stretching the truth or taking their measurements with an extreme stigmation or something.
  • pRK - Saturday, June 17, 2017 - link

    And what did Imtel did with their 26-28nm "feature size" Process Node, They call it 22nm. So nobody cares as long there's spare change in the pocket to buy these nibbles.
  • name99 - Tuesday, October 4, 2016 - link

    A full node shrink is by a factor of .7, density up by factor of 2 (naively).
    A half node shrink is by a factor of .9 density up by a factor of 1.2 (naively).

    https://en.wikipedia.org/wiki/Die_shrink#Half-shri...
  • name99 - Tuesday, October 4, 2016 - link

    But arguing about this is idiotic because the choices foundries make differ on multiple dimensions.
    The most obvious one right now is whether or not finFETs are offered (and exactly how they are structured), but there are other issues like 1D vs 2D routing, or how much flexibility is offered by metal layers.
    In the future more important than whether a node is "8 or 7 or 6 or 5" nm, and even more important than its density for a particular type of SRAM cell will be things like whether wraparound transistors are offered, or III-V materials.
  • JoeyJoJo123 - Monday, October 3, 2016 - link

    #nm refers to the minimum size of the transistors on that particular manufacturing process. As far as I know, it's no guarantee that _every_ transistor in a 14nm node process chip is exactly 14nm; some may be larger for a variety of reasons.

    Additionally, a chip isn't made of 100% transistors. There are substrates and such that the gates are built into that don't scale down as neatly as the transistor gates themselves. Likewise this article I found appears to discuss transistors and the way they shrink in better detail:

    http://www.extremetech.com/computing/190946-stop-o...

    "...comparing the size of each major SoC block (CPU, GPU, and cache) at 20nm against the Apple A7 at 28nm. This kind of fine-grained analysis reveals three entirely different scaling ratios between the two nodes — because not all transistors scale equally."
  • SleepyFE - Monday, October 3, 2016 - link

    The #nm usually tells you the width of the channel (don't know if that is still the case with FinFET), which is the smallest part of the transistor. So the transistor itself is bigger depending on the length of the channel, the size on p-doped silicone and n-doped and so on. Since it does not tell you the size of the transistor you can't really make good guesses as to the density of them. Also if i recall correctly when they made the jump to 28nm they had to space them further apart or you would get "crosstalk". Until they make it and tell you how many transistors there are on one chip you can't really do the math. They obviously can (hence the power saving figures) but they're not telling.
  • witeken - Wednesday, October 5, 2016 - link

    You are incorrect. The mm hasn't communicated any meaningful information for over 2 decades now.

    The channel width of all companies' 14/16nm is 8nm. But the channel width has nothing to do with density.
  • pRK - Saturday, June 17, 2017 - link

    You're almost correct except i dont understand what decades are?
  • pRK - Saturday, June 17, 2017 - link

    "refers to the minimum size of the transistors on that particular manufacturing process. As far as I know, it's no guarantee that _every_ transistor in a 14nm node process chip is exactly 14nm; some may be larger for a variety of reasons"

    It actually refers to nothing except slideware. Process node is refer to feature size, and you can always measure it differently.
  • witeken - Wednesday, October 5, 2016 - link

    You are correct, the density will be more than 2x, but likely not 4x. For instance, TSMC's 20nm was 1.9x compared to 28nm, and their 7nm will be 1.63x compared to 10nm.
  • Meteor2 - Monday, October 3, 2016 - link

    Fantastic article. Questions that popped into my head were answered as I read on.
  • ingwe - Monday, October 3, 2016 - link

    Yeah totally agree. It was great.

    Now I'm just hoping for no delays in production...
  • bji - Monday, October 3, 2016 - link

    Those two fab engineers looking at each other longingly in the wafer reflections is kind of cute.
  • lefty2 - Monday, October 3, 2016 - link

    > Those two fab engineers looking at each other longingly in the wafer reflections is kind of cute.
    Who says romance can't start on the fab floor?
  • pogostick - Monday, October 3, 2016 - link

    >Who says romance can't start on the fab floor?
    Not me, I've seen it happen.
  • Alexvrb - Monday, October 3, 2016 - link

    Die wafers, nature's aphrodisiac.
  • Agent Smith - Tuesday, October 4, 2016 - link

    ...they probably just want their glasses to be that big so they can see the traces.
  • jjj - Monday, October 3, 2016 - link

    You present EUV in the wrong light. It doesn't provide any miracles, it will be inserted when it becomes cheaper to use , that's all.
    You push TSMC 7nm to 2H 2018 and later in the article you move it to H1 where it should be.
    The info about 3 clients taped out on 10nm TSMC is half a year old so they should have more now.
    You list Qualcomm as a TSMC 10nm client and everything points out to them using Samsung so they can keep SD in Samsung's flagships. The 3rd name to tape out early is likely Huawei.
    The claim that TSMC would be behind on EUV is wrong, they'll insert it when it makes economic sense so on 7nm if possible just not from day one.
    You mention HPC clients but you don't make it clear that there are 3 versions of TSMC 7nm with one for HPC and one for auto.
    UMC has 14nm next year.
    You skip Intel but if Coffee Lake is on 14nm that would mean that Intel won't have very high wafer starts( 2c tiny area x not very high vols) on 10nm till 2019, excluding any big foundry wins.If that ends up to be true, one has to wonder about their costs.

    GloFo also claimed a 30% cost reduction over 14nm.
    Fin pitch in the 30nm range, 17 layers metal and 80-84 masks steps.
  • Meteor2 - Monday, October 3, 2016 - link

    Lol @ coffee lake. Perhaps that's what you need?

    Intel's plans are discussed in the article, and a little while ago there was another brilliant article all about EUV. You should search for it.
  • witeken - Wednesday, October 5, 2016 - link

    Intel will have millions of 10nm Cannonlake in the second half of next year. Laptop market is bigger than desktop.
  • ABR - Monday, October 3, 2016 - link

    Nice article, reminds me of the AnandTech of old.
  • Glideslope - Monday, October 3, 2016 - link

    Agreed. Sad to see all the hate in here. My son is Process Engineer at Fab 8. Sure it's not perfect, but he gives it 24/7, and I'm very proud of him.
  • ws3 - Tuesday, October 4, 2016 - link

    It isn't hate. it is sad realism based on historical performance. Your son could be the best process engineer in the world and still be dragged down by the failures of the organization he works for.
  • HighTech4US - Monday, October 3, 2016 - link

    GloFo can't even get Samsung's 14nm process right yet here you are stating that they will have 7nm in 2018 and EUV early.

    Yea right - pull the other one.
  • Alexvrb - Monday, October 3, 2016 - link

    How exactly did they not "get it right"?
  • HighTech4US - Tuesday, October 4, 2016 - link

    Reason for p*ss poor clocks on Polaris
  • sonicmerlin - Tuesday, October 4, 2016 - link

    That has to do with AMD's horribly inefficient arch that's badly in need of an overhaul.
  • CiccioB - Tuesday, October 4, 2016 - link

    We have seen problems with high clock also with Apple A8 SoC with respect to the same chip made by TMSC.
    So it may be an architectural problem (as seen on TMSC 28nm vs nvidia's architecture) but GF 14nm PP may have its contributions to the problem.
  • name99 - Tuesday, October 4, 2016 - link

    WTF are you talking about? "We have seen problems with high clock also with Apple A8 SoC"

    (a) A8 was shipped on TSMC 20nm. Nothing in common with GloFo 14nm.

    (b) There is absolutely no reason to believe that the A8 was clock-limited in an unexpected way by TSMC 20nm. The device performed better in every way than the A7, and better in every way than the competition.
    A far more sensible analysis is that it's not exactly trivial to redesign the pipeline of such a high performance processor (while retaining the IPC and low power characteristics) and to do that took them two years. The A8 was the interim processor that shipped (as minor tweaks and improvements on the A7) while the serious work on the A9 was done in parallel and took two years.
  • CiccioB - Wednesday, October 5, 2016 - link

    Yes, it was the A9, not A8.

    Your mind and neural reach are flexible like a stone, has no one ever told you?
  • name99 - Wednesday, October 5, 2016 - link

    So how does the A9 change things?
    Once again not on GF 14nm, once again no problems with clock rates or performance, once again outperforms (substantially) all competing chips.

    So we're back to WTF are you talking about? If the A9 represents some sort of problem in your world, it's a problem that every tech company on earth (including Intel) would love to have,
  • FriendlyUser - Tuesday, October 4, 2016 - link

    Anyone still believes announcements from GlobalFoundries? I'll believe it when I see actual product reviews. All they have done over the last few years is fail, taking some decent AMD designs with them.
  • StrangerGuy - Tuesday, October 4, 2016 - link

    GF is so awesome that a bottom feeder like AMD is trying their darndest to move their chips elsewhere and even Mediatek wouldn't want to touch them with a 100 foot pole.
  • CiccioB - Tuesday, October 4, 2016 - link

    Well, AMD has ported its GPU fabrication to GF from TMSC.
    I find it a desperate move to try to be improve their abmsysal efficiency, greatly failing as we have seen.
    However they are giving GF some confidence.
  • lefty2 - Tuesday, October 4, 2016 - link

    It's not clear where AMD make their GPUs. This is from an AnandTech article:
    "The group has confirmed that they will be utilizing both traditional partner TSMC’s 16nm process and AMD fab spin-off (and Samsung licensee) GlobalFoundries’ 14nm process, making this the first time that AMD’s graphics group has used more than a single fab. To be clear here there’s no expectation that RTG will be dual-sourcing – having both fabs produce the same GPU – but rather the implication is that designs will be split between the two fabs. To that end we know that the small Polaris GPU that RTG previewed will be produced by GlobalFoundries on their 14nm process, meanwhile it remains to be seen how the rest of RTG’s Polaris GPUs will be split between the fabs."
  • CiccioB - Tuesday, October 4, 2016 - link

    It remains that before Polaris ALL GPUs were produced by TMSC while now at least the cheapest ones are made by GF.
    So GF gives some advantages or AMD thought they could.

    It will be interest to see Vega if produced by TMSC. It will allow for direct comparison to nvidia's Pascal efficiency both in terms of area and of power consumption.
  • CiccioB - Tuesday, October 4, 2016 - link

    And to Volta as well...
  • CiccioB - Tuesday, October 4, 2016 - link

    Really profess article, really.
    All aspects are covered well and well explained.
  • CiccioB - Tuesday, October 4, 2016 - link

    BTW: if I write great article the server sees it as spam! :D
  • KAlmquist - Tuesday, October 4, 2016 - link

    According to one of the linked articles (specfically http://semiengineering.com/10nm-versus-7nm/), smaller nodes are significantly more expensive to design for.

    “It will take chip designers about 500 man-years to bring out a mid-range 7nm SoC to production,” Gartner’s Wang said. Therefore, a team of 50 engineers will need 10 years to complete the chip design to tape-out. In comparison, it could take 300 engineer-years to bring out a 10nm device, 200 for 14nm, and 100 for 28nm, according to Gartner.

    This seems a bit improbable to me, but if it is true it is another obstacle to moving to smaller node sized.
  • name99 - Tuesday, October 4, 2016 - link

    One thing I'm not sure of (and that never gets explained) is how static these numbers are.
    Yes, today, maybe it takes 500 man-years. But will it still takes 500 man-years in 2021, after lots of experience has been accumulated, and the design tools have all been improved?
  • CiccioB - Tuesday, October 4, 2016 - link

    What I see from the comparison table, is that if GF does not fulfill its promises (as it usually does not) and AMD does not really improves its efficiency on 7nm power efficiency of AMD GPUs would just be a bit better than current TMSC 16+nm, that just again a step behind as it is now with 14nm being equal (or even a little worse) than nvidia on 28nm.

    Die size may be an advantage over TMSC, but power and performance may really be an issue.
  • BrokenCrayons - Tuesday, October 4, 2016 - link

    A lot can change between now and 2018 when production ramps up and we start seeing availability in consumer electronics. It's interesting news, but nothing to get excited about...yet.
  • name99 - Tuesday, October 4, 2016 - link

    "Finally, TSMC does not seem to be afraid of multi-patterning and intends to produce semiconductors using DUV 7 nm manufacturing tech in 2H 2018."

    Where did you get that 2H 2018 from, Andrei?
    Everything I've seen suggests 1H 2018 (probably the Apple A11X).

    From SEPTEMBER 15TH, 2016:
    Still, TSMC hopes to be the first player to ramp up 7nm. “Our 7nm technology development is well on track,” said Mark Liu, president and co-CEO of TSMC, in a recent conference call. “(Customers) all have aggressive product tape-out plans in the first half 2017, with volume production planned in early 2018.”
  • witeken - Wednesday, October 5, 2016 - link

    You remember that TSMC once promised 20nm in early 2013, right? It launched in late 14.
  • name99 - Tuesday, October 4, 2016 - link

    "For example, Intel argues that transistor density of its 10 nm process is going to be comparable to transistor densities of competing 7 nm technologies. "

    Yeah, Andrei. Intel argues this because clueless rubs like you happily parrot anything Intel says.
    How are those Intel predictions working out?
    Remember that claim about how TSMC was going to struggle to reach 16nm, and the result would suck? Remember the grand claims for a Broadwell release that turned into a slow trickle of devices? Let's turn the clock back a year and see what was happening:
    http://wccftech.com/intel-10nm-ramp-canonlake-dela...

    How has the Intel roadmap been shifted over the past few years:
    http://wccftech.com/intel-10nm-cannonlake-ice-lake...

    That's Intel for you --- constant stream of new code names (to keep the clueless excited), constant stream of hype and claims, but also a constant stream of delayed products. (Coffee Lake? WTF??? Obviously a backup plan because they don't expect to get Cannonlake in volume even with the one year delay.)

    Meanwhile the company Intel keeps slagging, TSMC, just keeps its mouth shut and delivers. You can go back to 2012, 2013 and look at their roadmap, and they're pretty much following it on schedule. They don't waste their time rying to fake up graphs that make Intel look bad (not that they'd need to even fake them, given Intel's recent execution).

    But I digress. My point, Andrei, is that you are a journalist, and part of your job is to put this stuff in context, not to act as a mouthpiece for company PR. It's bad enough seeing political journalists happy to report whatever nonsense campaigns claim, without checking the facts; I don't need to see that likewise on tech blogs.

    I listed the numbers here:
    http://www.realworldtech.com/forum/?threadid=16099...
  • witeken - Wednesday, October 5, 2016 - link

    Wow, I've read a lot of mistakes in the comments of this article, but this is just the absolute worst!!

    When I go back to TSMC 2012 Roadmap, they were promising 20nm in early 13. Guess what, it arrived late 14. TSMC has such a bad track record of promising things. To be fair, things have improved since then, but I will believe it when I see it.

    In any case, it is absolutely true that Intel's 10nm will be about the same density as TSMC 7nm but launch much earlier, even with the delay to 2017.
  • Andrei Frumusanu - Friday, October 7, 2016 - link

    I know you have a chip on your shoulder against me, but maybe re-read the author's name on this piece.
  • name99 - Tuesday, October 4, 2016 - link

    "We have seen a few such nodes in the recent years: as a limited number of firms used 45 nm, 32 and 20 nm process technologies, albeit all for different reasons."

    "In general, GlobalFoundries positions its 22FDX as an alternative for 14/16 nm FinFET technologies"

    So let me get this straight. 20nm (in the hands of TSMC) is essentially a failure, a short lived node. But 22FDX (with exactly the same capabilities and costs, essentially, as 20nm) has great future ahead of it?

    Why not just admit the truth here?
    (a) The conventional wisdom decided that 20nm was dead when nV and ATI skipped it.
    (b) Even though the reason they skipped it had to do with technical issues VERY SPECIFIC to GPUs, and not especially relevant to other manufacturers.
    (c) And once the narrative was out there that 20nm was a failed node, it would have been just too humiliating to actually look into the numbers, draw the graphs, compare with the past, and admit that this particular hot take was BS from the start.

    These new nodes take YEARS to be adopted, then persist for years before they are phased out, for the obvious reason that most companies don't have the budget to redo their particular specialty chip every year on the immediately newest process. This means that anyone claiming to know that a process is unpopular before about three or four years have passed is talking out their ass.

    Once again, see the data here if you care:
    http://www.realworldtech.com/forum/?threadid=16099...
  • Haawser - Wednesday, February 1, 2017 - link

    22FDX is nothing like 20nm. It's back biased FD-SOI, not bulk planar. Most industry experts see it as 'the' solution for IoT, Wireless, ULP mobile etc.

    https://www.semiwiki.com/forum/content/6475-iedm-2...

    22FDX will be followed by 12FDX.
  • Anymoore - Wednesday, October 5, 2016 - link

    Chances are EUV will not be ready.
  • zodiacfml - Thursday, October 6, 2016 - link

    so that explains it, they just have no choice but to skip 10nm. that could be painful though as CPUs for server and mobile, and GPUs would require the latest process node to be competitive. Missing 2 or 3 years of competitiveness seems substantial, don't you think?

    this also explains Intel's tick tock tock tock model recently.

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