Samsung Foundry Updates: 7nm EUV, 10LPP, and 14LPCby Joshua Ho on April 22, 2016 5:00 AM EST
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Earlier this week, Samsung announced a number of updates on the foundry side of their business. While process technology might not be necessarily as interesting as the actual end product from a consumer perspective, it can often give us a good idea for what to expect in terms of performance and power from future products. Of course, it’s up to the various fabless chip design companies around the world to actually exploit the full potential of a process, but in general power and performance are often gated by process node. Almost everything in computing revolves around supporting abstractions, which inevitably means overhead to support these abstractions, so progress at the foundry level is critical for moving the industry forward as a whole.
The first, and probably most important announcements are related to process roadmap. The most important point that Samsung made here was that they fully intend to deploy extreme UV (EUV) in mass production for their 7nm processes, which is a pretty significant claim to make as even imec was reluctant to say that EUV would be happening at 7nm. However, those at Samsung seem to believe that this is necessary because otherwise the first metal interconnect layer would require triple patterning, and the transistors themselves would likely be facing similar multiple patterning requirements.
While we’ve discussed EUV before and the challenges that it faces, Samsung believes that triple patterning is not really a viable solution because the number of masks needed goes from roughly 60 or so with double patterning to 90 or so with triple patterning, which results in a steep increase in costs and long lead times for prototypes and production ramp as the masks are made with e-beam lithography for precision, so mispredict penalty for a design isn’t nearly as severe as it would be with a 7nm 193i-only process. Of course, EUV is only going to be used in critical layers, so 193i will still be used for the majority of the layers in the chip, but even so EUV will still be a major hurdle for Samsung to clear here as EUV sources still don’t have enough power to be viable for mass production. Interestingly, Samsung claims that they have mask inspection tools internally for EUV masks, which could help them get to deploying EUV sooner in mass production.
On 10nm, things are less murky as it’s pretty clear that this process will be able to mostly be scaling of the 14nm node to improve performance and possibly improve cost, so the primary update here is that 10LPP (Low Power Plus) will be following 10LPE (Low Power Early) for a 10% improvement in performance. A design done in 10LPE can be directly ported to 10LPP with no new design work.
At 14nm, Samsung seems to be doing well here as their fabs in Korea and Texas are running full time, with over 0.5M wafers shipped and defect density below 0.2 defects/cm^2 in production. This defect density is said to be highly competitive, but I’m not really qualified to say whether this is the case. The primary update of note at 14nm is that 14LPC will have an RF option by the end of the year to enable connectivity for applications like automotive and transceivers.
On the process side, 28nm is still pretty critical for a number of applications as this is the last process where planar is viable. Even if 20nm is technically the last planar process, it’s not all that attractive compared to 28nm due to cost, DIBL leakage, and sheer heat density. Samsung’s 28FDS process has been in mass production for some time now as a higher-end node designed to provide ~20nm FinFET class performance on 28nm, but the main news of note here is that 28FDS will have an RF process which adds elements like inductors and is properly characterized to allow for high speed electronics to work properly. 28FDS will also have embedded non-volatile flash memory to enable embedded applications where some memory is needed as a ROM. Kelvin Low of Samsung noted that FD-SOI is also notable for reducing soft error rate relative to bulk CMOS which reduces the need for design-level mitigations, although this was mostly in the context of safety-critical systems that could be seen in automotive and other segments.
On the design and packaging services side, Samsung is providing more here than before in the form of reference design flows for their 14nm process, and a similar flow will be available for 10nm. Packaging services that used to be for internal use only will also be opened up, with things like 2.5D interposers to enable HBM on GPUs and similar use cases, although it was noted that in that particular case the interposer is currently a bit too expensive for use outside of high-priced components like GPUs. Samsung is also providing some IP blocks for customers to speed up time to market for things like DDR4 and PCI-E controllers.
Overall, Samsung is seems to be quite aggressive on the foundry side and it’ll be interesting to see whether this pays off. Of course, there are the inevitable questions of whether this is comparable to Intel or TSMC’s process, but for now we can’t really say absent details about the pitches of the key layers, operating voltages, and other aspects that we need to consider in order to really compare process nodes. We saw how Samsung’s 14nm push paid off, so it’ll be interesting to see how things shake out with 7nm.
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clinton_goh - Friday, April 22, 2016 - linkThanks for the update. I was wondering if you could update the source for this? Link seems broken. Thanks.
clinton_goh - Friday, April 22, 2016 - linkIt's working now.
trane - Friday, April 22, 2016 - linkSamsung Foundry has been killing it of late. Remember when Intel used to be years ahead of the rest? In the short span of half a decade, Samsung has eliminated the gap completely, and clearly overtaken TSMC.
What is exciting is Globalfoundries and AMD has access to Samsung's tech. After decades, AMD might finally be ahead of Intel on process!
7nm is exciting though. Samsung's EUV versus Intel's silicon-replacement. I have a feeling someone is going to have a significant advantage.
T1beriu - Friday, April 22, 2016 - linkYou would be correct if Samsung's 14nm/10nm/7nm were equal to Intel's.
halcyon - Friday, April 22, 2016 - linkHow is Samsung's 14nm/10nm/7nm unequal to Intel's? Can you explain? I don't know.
CaedenV - Friday, April 22, 2016 - linkI am no expert (perhaps someone else can chime in), but my understanding is that when a company produces a '7nm' chip, then that 7nm can measure almost anything. It can be the size of the electronic structures, or the resolution at which it can 'print', or the spacing between structures, etc. etc. etc. Plus, not everything is going to be at 7nm, only certain parts will be. Often times it is only simple repeating structures that get the ultra small 7nm treatment, while other parts of the chip continue to have larger simpler processes applied to them so the failure count stays acceptable.
Plus, different processes at the same nm level have different results. Some bleed more electrons, some have more cross-talk and interferance within the chip, etc. etc. etc.
Long story short, not all 'nm' ratings are made equal, and while some companies are getting good at getting certain parts of a die shrunk down, Intel still holds the crown for having the smallest die size applied to the majority of their chips, while retaining a good failure rate, and with minimal other issues.
willis936 - Friday, April 22, 2016 - linkI'm not sure that's right. The nm length almost universally means the width of the channel in the transistors (sometimes called the smallest feature size). Also I'm not certain mixing nodes in a foundry happens very often but I simply don't know. It wouldn't make a lot of the previous transistor count estimations from die size and process make a lot of sense and those are usually accurate. Also if Samsung really is making transistors smaller than Intel then they do have a technological advantage. Things are not looking great for Intel atm. They won't die overnight but their mismanagement over the past decade will hurt them.
menting - Friday, April 22, 2016 - linkthat was true a few years back, but it's not true anymore.
tuxfool - Friday, April 22, 2016 - linkThe size rating is indeed the smallest feature size that can be printed and is usually applied to the channel width. However Transistors are more than a single dimension in size, these days they are even 3 dimensional.
Intel's process nodes while being nominally the same feature size in name, are much more dense and usually of a higher quality. For example both TSMC and Samsung/GF use 20nm level sizing for their metal layers at their 16/14nm nodes, whereas intel actually has 14nm sizing.
It should be noted that when talking about the sizing at this point they are just marketing names.
name99 - Friday, April 22, 2016 - link"Intel still holds the crown for having the smallest die size applied to the majority of their chips, while retaining a good failure rate, and with minimal other issues."
These are totally unfounded claims. There is no useful sense in which Intel has "smallest die size", we have no idea what Intel yields are compared to Samsung or TSMC, we have no idea what field failure rates are (but they are spectacularly low for all three companies), and there are no process-specific "other issues" that apply to some foundries and not others.
TSMC appears to have better ultra-tight packaging (InFO), and certainly it (and Samsung's) packaging is a lot more useful to its target customers insofar as it enables putting together packages from a variety of different chips. Intel does have a history of tight packages for the items it ships (starting from putting a separate L2 on the same package all those years ago), now with things like CrystalWell, but doesn't seem to be as flexible as TSMC, presumably because it hasn't needed to be.