Samsung and TSMC made several important announcements about the present and future of their semiconductor manufacturing technologies in March. Samsung revealed that it had shipped over 70 thousand wafers processed using its first-generation 10 nm FinFET fabrication process (10LPE) and also announced major additions to its upcoming manufacturing technology roadmap. In particular, the company plans to introduce three processes it has not talked about thus far. TSMC said that it is about to start mass production of ICs (integrated circuits) using its first-gen 10 nm technology and also announced several new processes that will be launched in the coming years, including its first 7 nm EUV process due in 2019.

10 nm: Samsung Is Shipping

Update 5/12: Samsung informed us that its press release from October, 2016, compares characteristics of the 10LPE manufacturing technology with those of the 14LPE, not 14LPP. The text and table have been updated accordingly.

Samsung said it had started to make SoCs using its 10LPE fabrication technology last October, which is something we already knew. This manufacturing process allowed the company to make its chips 30% smaller compared to ICs made using its 14LPE process as well as reducing power consumption by 40% (at the same frequency and complexity) or increase their frequency by 27% (at the same power and complexity). So far, Samsung has processed over 70 thousand wafers using its 10LPE technology, which can give an idea about Samsung’s 10 nm production capacities (considering that the whole 10 nm production cycle is greater than the 90 days we saw with previous-gen FinFET processes). At the same time, keep in mind that Samsung does not have many 10 nm designs to manufacture right now: we know only of the company’s own Exynos 9 Octa 8895 as well as Qualcomm’s Snapdragon 835 seen in the Samsung Galaxy S8.

Advertised PPA Improvements of New Process Technologies
Data announced by companies during conference calls, press briefings and in press releases
  GF Samsung
7nm DUV
vs 14LPP
vs 28LPP
vs 14LPE
vs 14LPP
vs 10LPE
Power >60% 60% 40% 30% ~15% ?
Performance >30% 40% 27% >10% ~10% ?
Area Reduction >50% 50% 30% 30% none ?

In addition to its production milestone, Samsung also confirmed plans to start mass production of chips using its second-generation 10 nm manufacturing process called 10LPP (10 nm low-power plus) by the end of 2017 as well as its third-generation 10 nm technology called 10LPU by the end of 2018. Samsung said last year that the 10LPP is going to enable a ~10% performance increase (at the same power and at the same complexity) versus the 10LPE, but we know absolutely nothing about the 10LPU. It is logical to assume that the 10LPU will bring certain PPA-related (performance, power, area) improvements, but it is not clear how Samsung plans to achieve them and which one of the three will be the focus for improvements. As it appears, just like Intel, Samsung has ended up with three generations of 14 nm fabrication processes and is going to end up with three generations of 10 nm manufacturing technologies. It is noteworthy that Samsung itself does not use its 14LPC (low-power compact) for its leading edge SoCs, which may suggest that the 10LPU is also not aimed at this segment of the market. In fact, it is highly likely that the 10LPU will target ultra-small and ultra-low-power ICs for various emerging devices, but Samsung yet has to confirm that.

10nm: TSMC Is Steady

As for TSMC, its 10 nm process technology (CLN10FF) is now qualified for production at the company’s GigaFabs 12 and 15, where high-volume ramp is expected to start in H2 2017. Production capacity of these two fabs is hundreds of thousands wafer starts per quarter and TSMC plans to ship 400 thousand wafers processed using its 10 nm manufacturing tech this year. Considering the long production cycles for FinFET-based technologies, it is about time for TSMC to start ramping up 10 nm so to be able to supply enough chips to its main customer in time. Apple is expected to launch its new iPhone products in September or October and needs to get SoCs couple of months before the launch.

Advertised PPA Improvements of New Process Technologies
Data announced by companies during conference calls, press briefings and in press releases
Power 70% 60% 40% 60% <40%
Performance 65% 40% 20% 30% ?
Area Reduction ~50% none >50% 70% >37%

PPA advantages of TSMC’s CLN10FF over its CLN16FF+ (second-gen 16 nm) have been discussed already and they are significant for developers of mobile SoCs (but not that significant for makers of other ICs): a ~50% higher transistor density, a 20% performance improvement at the same power and complexity or a 40% lower power consumption at the same frequency and complexity. Unlike Samsung, TSMC does not seem to plan multiple generations of 10 nm and will go straight to 7 nm next year. 7nm is currently very popular among chip designers, indicating a future major milestone. However, in addition to the CLN7FF, the company will also offer several other manufacturing technologies for ultra-small and ultra-low-power applications.

Beyond 10 nm at TSMC: 7 nm DUV and 7 nm EUV
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  • SuperMecha - Saturday, May 6, 2017 - link

    “First of all, neither he, or anyone else outside those companies actually knows enough about the actual chips to know the true density.”

    That’s grossly false. Their customers (i.e. AMD, Nvidia, Qualcomm, etc.) need to have the PDKs to design their chips. The PDKs will contain the design rules and ultimately the transistor specifications necessary to design a chip for that process. TSMC will be accepting 7nm tape outs this quarter which means the transistor specifications were likely frozen some time ago. Never mind the fact that the companies have released details of their future process nodes.
  • Wilco1 - Sunday, May 7, 2017 - link

    I guess you also don't believe then that both TSMCs and GF's 16/14nm processes are already denser than Intel's 14nm? See eg. Apple A8 on 20nm was shown to be much denser than Core M on 14nm.

    Whatever the marketing claims say, Intel is already behind on density in actual designs. Intel's latest 14nm process is even less dense. So what makes you think that Intel could catch up?
  • melgross - Wednesday, May 10, 2017 - link

    Because what you're saying is wrong. I haven't read anything saying that intels's process is less dense.
  • Wilco1 - Thursday, May 11, 2017 - link

    Well the link I provided shows it very clearly - I presume you didn't read it?

    Intel may have better CPP/MP/FP/SRAM at 14nm vs TSMC/GF, but AMD still gets better L2 and L3 density despite the less advanced process. And density on real designs matters more than the process marketing numbers (which are about bragging rights, but don't tell the whole story).
  • lefty2 - Sunday, May 7, 2017 - link

    Scott's analysis was actually spot on. Dick James of TechInsights actually measured Samsungs 10nm chip:
    measuring a 68 mm contacted gate pitch, 51 nm metal pitch, dual STI and single dummy gate.
    That's compared to Intel's 14nm of 70 nm CPP x 52 nm MMP

    By comparison: Intel's 14nm is 70 nm CPP x 52 nm MMP.
  • sc14s - Friday, May 5, 2017 - link

    Seems to me past 2025 or so what are they going to do to compete assuming you hit that ~5nm and then iterate a few times on that process to maximize it's potential?
    You can't really go any further without some major physics breakthrough. it's kinda a race to the bottom just in a physics sense instead of the financial price slashing sense.
  • melgross - Friday, May 5, 2017 - link

    Most of the work has been with carbon nanotubes, with both IBM and Hp showing progress. But it's not expected to go commercial (if ever, really) before the mid 2020s, or possibly (more likely), the later part of the decade.

    So there will be a gap. Software developers will need to improve their software to improve performance finally, which should be a big benefit for everything.
  • bji - Friday, May 5, 2017 - link

    Regular hardware speed increases have allowed more software to be produced across a broader range of products more quickly because developers don't have to spend their time optimizing for performance as much because the hardware gets them to a 'good enough' place easily. Once the hardware is not getting faster, for every problem that requires greater performance, you simply shift more of the cost of creating the product to the software side. It will take longer to produce programs as a result. There is no free lunch; it's not like software development could have for no extra cost added more performance and now that hardware stops increasing in speed software development will just start adding that free performance in. The cost of producing software will just go up for that segment of the software market that is performance sensitive. Of course, quite a lot of the market is not performance sensitive so there will be little appreciable impact on most of the software market.
  • tarqsharq - Friday, May 5, 2017 - link

    It would be quite the time to be a skilled software developer though.

    A next generation John Carmack? Using computing tricks to pull off things that traditionally would bog down the available hardware?
  • vladx - Friday, May 5, 2017 - link

    You're assuming that there are real solutions that could revolutionize software performance and scalability, just like the P versus NP problem we might never get an answer to that.

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